Search results for: average power dissipation.
4280 Leakage Reduction ONOFIC Approach for Deep Submicron VLSI Circuits Design
Authors: Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj
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Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.
Keywords: Deep submicron, Leakage Current, LECTOR, ONOFIC, Power Delay Product
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 24864279 Designing of Full Adder Using Low Power Techniques
Authors: Shashank Gautam
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This paper proposes techniques like MT CMOS, POWER GATING, DUAL STACK, GALEOR and LECTOR to reduce the leakage power. A Full Adder has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of Full Adder. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a large extent.
Keywords: Low Power, MT CMOS, Galeor, Lector, Power Gating, Dual Stack, Full Adder.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 21084278 Explicit Delay and Power Estimation Method for CMOS Inverter Driving on-Chip RLC Interconnect Load
Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar
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The resistive-inductive-capacitive behavior of long interconnects which are driven by CMOS gates are presented in this paper. The analysis is based on the ¤Ç-model of a RLC load and is developed for submicron devices. Accurate and analytical expressions for the output load voltage, the propagation delay and the short circuit power dissipation have been proposed after solving a system of differential equations which accurately describe the behavior of the circuit. The effect of coupling capacitance between input and output and the short circuit current on these performance parameters are also incorporated in the proposed model. The estimated proposed delay and short circuit power dissipation are in very good agreement with the SPICE simulation with average relative error less than 6%.Keywords: Delay, Inverter, Short Circuit Power, ¤Ç-Model, RLCInterconnect, VLSI
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 16804277 Reduction of Leakage Power in Digital Logic Circuits Using Stacking Technique in 45 Nanometer Regime
Authors: P.K. Sharma, B. Bhargava, S. Akashe
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Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.
Keywords: Stack, 6T SRAM cell, low power, threshold voltage
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 34104276 Efficiency Enhancement of PWM Controlled Water Electrolysis Cells
Authors: S.K. Mazloomi, Nasri b. Sulaiman
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By analyzing the sources of energy and power loss in PWM (Pulse Width Modulation) controlled drivers of water electrolysis cells, it is possible to reduce the power dissipation and enhance the efficiency of such hydrogen production units. A PWM controlled power driver is based on a semiconductor switching element where its power dissipation might be a remarkable fraction of the total power demand of an electrolysis system. Power dissipation in a semiconductor switching element is related to many different parameters which could be fitted into two main categories: switching losses and conduction losses. Conduction losses are directly related to the built, structure and capabilities of a switching device itself and indeed the conditions in which the element is handling the switching application such as voltage, current, temperature and of course the fabrication technology. On the other hand, switching losses have some other influencing variables other than the mentioned such as control system, switching method and power electronics circuitry of the PWM power driver. By analyzings the characteristics of recently developed power switching transistors from different families of Bipolar Junction Transistors (BJT), Metal Oxide Semiconductor Field Effect Transistors (MOSFET) and Insulated Gate Bipolar Transistors (IGBT), some recommendations are made in this paper which are able to lead to achieve higher hydrogen production efficiency by utilizing PWM controlled water electrolysis cells.Keywords: Power switch, PWM, Semiconductor switch, Waterelectrolysis
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 34574275 Electrical Analysis of Corn Oil as an Alternative to Mineral Oil in Power Transformers
Authors: E. Taslak, C. Kocatepe, O. Arıkan, C. F. Kumru
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In insulation and cooling of power transformers various liquids are used. Mineral oils have wide availability and low cost. However, they have a poor biodegradability potential and lower fire point in comparison with other insulating liquids. Use of a liquid having high biodegradability is important due to environmental consideration. This paper investigates edible corn oil as an alternative to mineral oil. Various properties of mineral and corn oil like breakdown voltage, dissipation factor, relative dielectric constant, power loss and resistivity were measured according to different standards.Keywords: Breakdown voltage, corn oil, dissipation factor, mineral oil, power loss, relative dielectric constant, resistivity.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 31654274 Hot Workability of High Strength Low Alloy Steels
Authors: Seok Hong Min, Jung Ho Moon, Woo Young Jung, Tae Kwon Ha
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The hot deformation behavior of high strength low alloy (HSLA) steels with different chemical compositions under hot working conditions in the temperature range of 900 to 1100℃ and strain rate range from 0.1 to 10 s-1 has been studied by performing a series of hot compression tests. The dynamic materials model has been employed for developing the processing maps, which show variation of the efficiency of power dissipation with temperature and strain rate. Also the Kumar-s model has been used for developing the instability map, which shows variation of the instability for plastic deformation with temperature and strain rate. The efficiency of power dissipation increased with decreasing strain rate and increasing temperature in the steel with higher Cr and Ti content. High efficiency of power dissipation over 20 % was obtained at a finite strain level of 0.1 under the conditions of strain rate lower than 1 s-1 and temperature higher than 1050 ℃ . Plastic instability was expected in the regime of temperatures lower than 1000 ℃ and strain rate lower than 0.3 s-1. Steel with lower Cr and Ti contents showed high efficiency of power dissipation at higher strain rate and lower temperature conditions.Keywords: High strength low alloys steels, hot workability, Dynamic materials model, Processing maps.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 20124273 Effects of Channel Bed Slope on Energy Dissipation of Different Types of Piano Key Weir
Authors: Munendra Kumar, Deepak Singh
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The present investigation aims to study the effect of channel bed slopes on energy dissipation across the different types of Piano Key Weir (PK weir or PKW) under the free-flow conditions in rigid rectangular channels. To this end, three different types (type-A, type-B, and type-C) of PKW models were tested and examined. To document and quantify this experimental investigation, a total of 270 tests were performed, including detailed observations of the flow field. The results show that the energy dissipation of all PKW models increases with the bed slopes and decreases with increasing the discharge over the weirs. In addition, the energy dissipation over the PKW varies significantly with the geometry of the weir. The type-A PKW has shown the highest energy dissipation than the other PKWs. As the bottom slope changed from Sb = 0% to 1.25%, the energy dissipation increased by about 8.5%, 9.1%, and 10.55% for type-A, type-B, and type-C, respectively.
Keywords: Piano key weir, bed slope, energy dissipation across PKW, free overfalls.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 4944272 Numerical Comparison of Rushton Turbine and CD-6 Impeller in Non-Newtonian Fluid Stirred Tank
Authors: Akhilesh Khapre, Basudeb Munshi
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A computational fluid dynamics simulation is done for non-Newtonian fluid in a baffled stirred tank. The CMC solution is taken as non-Newtonian shear thinning fluid for simulation. The Reynolds Average Navier Stocks equation with steady state multi reference frame approach is used to simulate flow in the stirred tank. The turbulent flow field is modelled using realizable k-ε turbulence model. The simulated velocity profiles of Rushton turbine is validated with literature data. Then, the simulated flow field of CD-6 impeller is compared with the Rushton turbine. The flow field generated by CD-6 impeller is less in magnitude than the Rushton turbine. The impeller global parameter, power number and flow number, and entropy generation due to viscous dissipation rate is also reported.
Keywords: Computational fluid dynamics, non-Newtonian, Rushton turbine, CD-6 impeller, power number, flow number, viscous dissipation rate.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 41324271 Design and Analysis of a Low Power High Speed 1 Bit Full Adder Cell Based On TSPC Logic with Multi-Threshold CMOS
Authors: Ankit Mitra
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An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.
Keywords: CMOS, TSPC, MTCMOS, ALU, Clock gating, power gating, pipelining.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 30644270 Transient Analysis & Performance Estimation of Gate Inside Junctionless Transistor (GI-JLT)
Authors: Sangeeta Singh, Pankaj Kumar, P. N. Kondekar
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In this paper, the transient device performance analysis of n-type Gate Inside JunctionLess Transistor (GI-JLT) has been evaluated. 3-D Bohm Quantum Potential (BQP) transport device simulation has been used to evaluate the delay and power dissipation performance. GI-JLT has a number of desirable device parameters such as reduced propagation delay, dynamic power dissipation, power and delay product, intrinsic gate delay and energy delay product as compared to Gate-all-around transistors GAA-JLT. In addition to this, various other device performance parameters namely, on/off current ratio, short channel effects (SCE), transconductance Generation Factor (TGF) and unity gain cut-off frequency (fT ) and subthreshold slope (SS) of the GI-JLT and GAA-JLT have been analyzed and compared. GI-JLT shows better device performance characteristics than GAA-JLT for low power and high frequency applications, because of its larger gate electrostatic control on the device operation.
Keywords: Gate-inside junctionless transistor GI-JLT, Gate-all-around junctionless transistor GAA-JLT, propagation delay, power delay product.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 24304269 Thermal Management of Space Power Electronics using TLM-3D
Authors: R. Hocine, K. Belkacemi, A. Boukortt, A. Boudjemai
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When designing satellites, one of the major issues aside for designing its primary subsystems is to devise its thermal. The thermal management of satellites requires solving different sets of issues with regards to modelling. If the satellite is well conditioned all other parts of the satellite will have higher temperature no matter what. The main issue of thermal modelling for satellite design is really making sure that all the other points of the satellite will be within the temperature limits they are designed. The insertion of power electronics in aerospace technologies is becoming widespread and the modern electronic systems used in space must be reliable and efficient with thermal management unaffected by outer space constraints. Many advanced thermal management techniques have been developed in recent years that have application in high power electronic systems. This paper presents a Three-Dimensional Modal Transmission Line Matrix (3D-TLM) implementation of transient heat flow in space power electronics. In such kind of components heat dissipation and good thermal management are essential. Simulation provides the cheapest tool to investigate all aspects of power handling. The 3DTLM has been successful in modeling heat diffusion problems and has proven to be efficient in terms of stability and complex geometry. The results show a three-dimensional visualisation of self-heating phenomena in the device affected by outer space constraints, and will presents possible approaches for increasing the heat dissipation capability of the power modules.
Keywords: Thermal management, conduction, heat dissipation, CTE, ceramic, heat spreader, nodes, 3D-TLM.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 27774268 Noise Optimization Techniques for 1V 1GHz CMOS Low-Noise Amplifiers Design
Authors: M. Zamin Khan, Yanjie Wang, R. Raut
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A 1V, 1GHz low noise amplifier (LNA) has been designed and simulated using Spectre simulator in a standard TSMC 0.18um CMOS technology.With low power and noise optimization techniques, the amplifier provides a gain of 24 dB, a noise figure of only 1.2 dB, power dissipation of 14 mW from a 1 V power supply.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 24434267 Energy Efficiency Testing of Fluorescent and WOLED (White Organic LED)
Authors: Hari Maghfiroh, Harry Prabowo
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WOLED is widely used as lighting for high efficacy and little power consumption. In this research, power factor testing between WOLED and fluorescent lamp to see which one is more efficient in consuming energy. Since both lamps use semiconductor components, so calculation of the power factor need to consider the effects of harmonics. Harmonic make bigger losses. The study is conducted by comparing the value of the power factor regardless of harmonics (DPF) and also by included the harmonics (TPF). The average value of DPF of fluorescent is 0.953 while WOLED is 0.972. The average value of TPF of fluorescent is 0.717 whereas WOLED is 0.933. So from the review of power factor WOLED is more energy efficient than fluorescent lamp.
Keywords: Fluorescent, harmonic, power factor, WOLED.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 15634266 Security over OFDM Fading Channels with Friendly Jammer
Authors: Munnujahan Ara
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In this paper, we investigate the effect of friendly jamming power allocation strategies on the achievable average secrecy rate over a bank of parallel fading wiretap channels. We investigate the achievable average secrecy rate in parallel fading wiretap channels subject to Rayleigh and Rician fading. The achievable average secrecy rate, due to the presence of a line-of-sight component in the jammer channel is also evaluated. Moreover, we study the detrimental effect of correlation across the parallel sub-channels, and evaluate the corresponding decrease in the achievable average secrecy rate for the various fading configurations. We also investigate the tradeoff between the transmission power and the jamming power for a fixed total power budget. Our results, which are applicable to current orthogonal frequency division multiplexing (OFDM) communications systems, shed further light on the achievable average secrecy rates over a bank of parallel fading channels in the presence of friendly jammers.
Keywords: Fading parallel channels, Wire-tap channel, OFDM, Secrecy capacity, Power allocation.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 22404265 A High Thermal Dissipation Performance Polyethyleneterephthalate Heat Pipe
Authors: Chih-Chieh Chen, Chih-Hao Chen, Guan-Wei Wu, Sih-Li Chen
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A high thermal dissipation performance polyethylene terephthalate heat pipe has been fabricated and tested in this research. Polyethylene terephthalate (PET) is used as the container material instead of copper. Copper mesh and methanol are sealed in the middle of two PET films as the wick structure and working fluid. Although the thermal conductivity of PET (0.15-0.24 W/m·K) is much smaller than copper (401 W/m·K), the experiment results reveal that the PET heat pipe can reach a minimum thermal resistance of 0.146 (oC/W) and maximum effective thermal conductivity of 18,310 (W/m·K) with 36.9 vol% at 26 W input power. However, when the input power is larger than 30 W, the laminated PET will debond due to the high vapor pressure of methanol.
Keywords: PET, heat pipe, thermal resistance, effective thermal conductivity.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 29744264 Power Efficiency Characteristics of Magnetohydrodynamic Thermodynamic Gas Cycle
Authors: Mahmoud Huleihil
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In this study, the performance of a thermodynamic gas cycle of magnetohydrodynamic (MHD) power generation is considered and presented in terms of power efficiency curves. The dissipation mechanisms considered include: fluid friction modeled by means of the isentropic efficiency of the compressor, heat transfer leakage directly from the hot reservoir to the cold heat reservoir, and constant velocity of the MHD generator. The study demonstrates that power and efficiency vanish at the extremes of both slow and fast operating conditions. These points are demonstrated on power efficiency curves and the locus of efficiency at maximum power and the locus of maximum efficiency. Qualitatively, the considered loss mechanisms have a similar effect on the efficiency at maximum power operation and on maximum efficiency operation, thus these efficiencies are reduced, even for small values of the loss mechanisms.
Keywords: Magnetohydrodynamic generator, electrical efficiency, maximum power, maximum efficiency, heat engine.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 7004263 RF Power Consumption Emulation Optimized with Interval Valued Homotopies
Authors: Deogratius Musiige, François Anton, Vital Yatskevich, Laulagnet Vincent, Darka Mioc, Nguyen Pierre
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This paper presents a methodology towards the emulation of the electrical power consumption of the RF device during the cellular phone/handset transmission mode using the LTE technology. The emulation methodology takes the physical environmental variables and the logical interface between the baseband and the RF system as inputs to compute the emulated power dissipation of the RF device. The emulated power, in between the measured points corresponding to the discrete values of the logical interface parameters is computed as a polynomial interpolation using polynomial basis functions. The evaluation of polynomial and spline curve fitting models showed a respective divergence (test error) of 8% and 0.02% from the physically measured power consumption. The precisions of the instruments used for the physical measurements have been modeled as intervals. We have been able to model the power consumption of the RF device operating at 5MHz using homotopy between 2 continuous power consumptions of the RF device operating at the bandwidths 3MHz and 10MHz.
Keywords: Radio frequency, high power amplifier, baseband, LTE, power, emulation, homotopy, interval analysis, Tx power, register-transfer level.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 17934262 Robust & Energy Efficient Universal Gates for High Performance Computer Networks at 22nm Process Technology
Authors: M. Geetha Priya, K. Baskaran, S. Srinivasan
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Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.
Keywords: Low power, CMOS, pass-transistor, flash memory, logic gates.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 24204261 Influence of Insulation System Methods on Dissipation Factor and Voltage Endurance
Authors: Farzad Yavari, Hamid Chegini, Saeed Lotfi
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This paper reviews the comparison of Resin Rich (RR) and Vacuum Pressure Impregnation (VPI) insulation system qualities for stator bar of rotating electrical machines. Voltage endurance and tangent delta are two diagnostic tests to determine the quality of insulation systems. The paper describes the trend of dissipation factor while performing voltage endurance test for different stator bar samples made with RR and VPI insulation system methods. Some samples were made with the same strands and insulation thickness but with different main wall material to prove the influence of insulation system methods on stator bar quality. Also, some of the samples were subjected to voltage at the temperature of their insulation class, and their dissipation factor changes were measured and studied.
Keywords: Vacuum pressure impregnation, resin rich, insulation, stator bar, dissipation factor, voltage endurance.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 5774260 Curbing Abuses of Legal Power in the Society
Authors: Tajudeen Ojo Ibraheem
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In a world characterized by greed and the lust for power and its attendant trappings, abuse of legal power is nothing new to most of us. Legal abuses of power abound in all fields of human endeavour. Accounts of such abuses dominate the mass media and for the average individual, no single day goes by without his getting to hear about at least one such occurrence. This paper briefly looks at the meaning of legal power, what legal abuse is all about, its causes, and some of its manifestations in the society. Its consequences will also be discussed and some suggestions for reform will be made. In the course of the paper, references will be made to various jurisdictions around the world.Keywords: Abuse, legal, power, society.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 20034259 Zero-Dissipative Explicit Runge-Kutta Method for Periodic Initial Value Problems
Authors: N. Senu, I. A. Kasim, F. Ismail, N. Bachok
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In this paper zero-dissipative explicit Runge-Kutta method is derived for solving second-order ordinary differential equations with periodical solutions. The phase-lag and dissipation properties for Runge-Kutta (RK) method are also discussed. The new method has algebraic order three with dissipation of order infinity. The numerical results for the new method are compared with existing method when solving the second-order differential equations with periodic solutions using constant step size.
Keywords: Dissipation, Oscillatory solutions, Phase-lag, Runge- Kutta methods.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 18964258 Energy Loss at Drops using Neuro Solutions
Authors: Farzin Salmasi
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Energy dissipation in drops has been investigated by physical models. After determination of effective parameters on the phenomenon, three drops with different heights have been constructed from Plexiglas. They have been installed in two existing flumes in the hydraulic laboratory. Several runs of physical models have been undertaken to measured required parameters for determination of the energy dissipation. Results showed that the energy dissipation in drops depend on the drop height and discharge. Predicted relative energy dissipations varied from 10.0% to 94.3%. This work has also indicated that the energy loss at drop is mainly due to the mixing of the jet with the pool behind the jet that causes air bubble entrainment in the flow. Statistical model has been developed to predict the energy dissipation in vertical drops denotes nonlinear correlation between effective parameters. Further an artificial neural networks (ANNs) approach was used in this paper to develop an explicit procedure for calculating energy loss at drops using NeuroSolutions. Trained network was able to predict the response with R2 and RMSE 0.977 and 0.0085 respectively. The performance of ANN was found effective when compared to regression equations in predicting the energy loss.Keywords: Air bubble, drop, energy loss, hydraulic jump, NeuroSolutions
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 16324257 Effect of Peak-to-Average Power Ratio Reduction on the Multicarrier Communication System Performance Parameters
Authors: Sanjay Singh, M Sathish Kumar, H. S Mruthyunjaya
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Multicarrier transmission system such as Orthogonal Frequency Division Multiplexing (OFDM) is a promising technique for high bit rate transmission in wireless communication system. OFDM is a spectrally efficient modulation technique that can achieve high speed data transmission over multipath fading channels without the need for powerful equalization techniques. However the price paid for this high spectral efficiency and less intensive equalization is low power efficiency. OFDM signals are very sensitive to nonlinear effects due to the high Peak-to-Average Power Ratio (PAPR), which leads to the power inefficiency in the RF section of the transmitter. This paper investigates the effect of PAPR reduction on the performance parameter of multicarrier communication system. Performance parameters considered are power consumption of Power Amplifier (PA) and Digital-to-Analog Converter (DAC), power amplifier efficiency, SNR of DAC and BER performance of the system. From our analysis it is found that irrespective of PAPR reduction technique being employed, the power consumption of PA and DAC reduces and power amplifier efficiency increases due to reduction in PAPR. Moreover, it has been shown that for a given BER performance the requirement of Input-Backoff (IBO) reduces with reduction in PAPR.Keywords: BER, Crest Factor (CF), Digital-to-Analog Converter(DAC), Input-Backoff (IBO), Orthogonal Frequency Division Multiplexing(OFDM), Peak-to-Average Power Ratio (PAPR), PowerAmplifier efficiency, SNR
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 32774256 Analysis of Performance of 3T1D Dynamic Random-Access Memory Cell
Authors: Nawang Chhunid, Gagnesh Kumar
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On-chip memories consume a significant portion of the overall die space and power in modern microprocessors. On-chip caches depend on Static Random-Access Memory (SRAM) cells and scaling of technology occurring as per Moore’s law. Unfortunately, the scaling is affecting stability, performance, and leakage power which will become major problems for future SRAMs in aggressive nanoscale technologies due to increasing device mismatch and variations. 3T1D Dynamic Random-Access Memory (DRAM) cell is a non-destructive read DRAM cell with three transistors and a gated diode. In 3T1D DRAM cell gated diode (D1) acts as a storage device and also as an amplifier, which leads to fast read access. Due to its high tolerance to process variation, high density, and low cost of memory as compared to 6T SRAM cell, it is universally used by the advanced microprocessor for on chip data and program memory. In the present paper, it has been shown that 3T1D DRAM cell can perform better in terms of fast read access as compared to 6T, 4T, 3T SRAM cells, respectively.Keywords: DRAM cell, read access time, tanner EDA tool write access time and retention time, average power dissipation.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 13304255 A Case Study of Limited Dynamic Voltage Frequency Scaling in Low-Power Processors
Authors: Hwan Su Jung, Ahn Jun Gil, Jong Tae Kim
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Power management techniques are necessary to save power in the microprocessor. By changing the frequency and/or operating voltage of processor, DVFS can control power consumption. In this paper, we perform a case study to find optimal power state transition for DVFS. We propose the equation to find the optimal ratio between executions of states while taking into account the deadline of processing time and the power state transition delay overhead. The experiment is performed on the Cortex-M4 processor, and average 6.5% power saving is observed when DVFS is applied under the deadline condition.
Keywords: Deadline, Dynamic Voltage Frequency Scaling, Power State Transition.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 9484254 Effect of Viscous Dissipation and Axial Conduction in Thermally Developing Region of the Channel Partially Filled with a Porous Material Subjected to Constant Wall Heat Flux
Authors: D Bhargavi, J. Sharath Kumar Reddy
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The present investigation has been undertaken to assess the effect of viscous dissipation and axial conduction on forced convection heat transfer in the entrance region of a parallel plate channel with the porous insert attached to both walls of the channel. The flow field is unidirectional. Flow in the porous region corresponds to Darcy-Brinkman model and the clear fluid region to that of plane Poiseuille flow. The effects of the parameters Darcy number, Da, Peclet number, Pe, Brinkman number, Br and a porous fraction γp on the local heat transfer coefficient are analyzed graphically. Effects of viscous dissipation employing the Darcy model and the clear fluid compatible model have been studied.
Keywords: Porous material, channel partially filled with a porous material, axial conduction, viscous dissipation.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 6294253 Power Saving System in Green Data Center
Authors: Joon-young Jung, Dong-oh Kang, Chang-seok Bae
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Power consumption is rapidly increased in data centers because the number of data center is increased and more the scale of data center become larger. Therefore, it is one of key research items to reduce power consumption in data center. The peak power of a typical server is around 250 watts. When a server is idle, it continues to use around 60% of the power consumed when in use, though vendors are putting effort into reducing this “idle" power load. Servers tend to work at only around a 5% to 20% utilization rate, partly because of response time concerns. An average of 10% of servers in their data centers was unused. In those reason, we propose dynamic power management system to reduce power consumption in green data center. Experiment result shows that about 55% power consumption is reduced at idle time.Keywords: Data Center, Green IT, Management Server, Power Saving.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 16164252 New Gate Stack Double Diffusion MOSFET Design to Improve the Electrical Performances for Power Applications
Authors: Z. Dibi, F. Djeffal, N. Lakhdar
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In this paper, we have developed an explicit analytical drain current model comprising surface channel potential and threshold voltage in order to explain the advantages of the proposed Gate Stack Double Diffusion (GSDD) MOSFET design over the conventional MOSFET with the same geometric specifications that allow us to use the benefits of the incorporation of the high-k layer between the oxide layer and gate metal aspect on the immunity of the proposed design against the self-heating effects. In order to show the efficiency of our proposed structure, we propose the simulation of the power chopper circuit. The use of the proposed structure to design a power chopper circuit has showed that the (GSDD) MOSFET can improve the working of the circuit in terms of power dissipation and self-heating effect immunity. The results so obtained are in close proximity with the 2D simulated results thus confirming the validity of the proposed model.Keywords: Double-Diffusion, modeling, MOSFET, power.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 15744251 Correlation between Capacitance and Dissipation Factor used for Assessment of Stator Insulation
Authors: José Luis Oslinger, Luis Carlos Castro
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Measurements of capacitance C and dissipation factor tand of the stator insulation system provide useful information about internal defects within the insulation. The index k is defined as the proportionality constant between the changes at high voltage of capacitance DC and of the dissipation factor Dtand . DC and Dtand values were highly correlated when small flat defects were within the insulation and that correlation was lost in the presence of large narrow defects like electrical treeing. The discrimination between small and large defects is made resorting to partial discharge PD phase angle analysis. For the validation of the results, C and tand measurements were carried out in a 15MVA 4160V steam turbine turbogenerator placed in a sugar mill. In addition, laboratory test results obtained by other authors were analyzed jointly. In such laboratory tests, model coil bars subjected to thermal cycling resulted highly degraded and DC and Dtand values were not correlated. Thus, the index k could not be calculated.Keywords: Aging, capacitance, dissipation factor, electrical treeing, insulation condition, partial discharge.
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