Analysis of Performance of 3T1D Dynamic Random-Access Memory Cell

Authors: Nawang Chhunid, Gagnesh Kumar

Abstract:

On-chip memories consume a significant portion of the overall die space and power in modern microprocessors. On-chip caches depend on Static Random-Access Memory (SRAM) cells and scaling of technology occurring as per Moore’s law. Unfortunately, the scaling is affecting stability, performance, and leakage power which will become major problems for future SRAMs in aggressive nanoscale technologies due to increasing device mismatch and variations. 3T1D Dynamic Random-Access Memory (DRAM) cell is a non-destructive read DRAM cell with three transistors and a gated diode. In 3T1D DRAM cell gated diode (D1) acts as a storage device and also as an amplifier, which leads to fast read access. Due to its high tolerance to process variation, high density, and low cost of memory as compared to 6T SRAM cell, it is universally used by the advanced microprocessor for on chip data and program memory. In the present paper, it has been shown that 3T1D DRAM cell can perform better in terms of fast read access as compared to 6T, 4T, 3T SRAM cells, respectively.

Keywords: DRAM cell, read access time, tanner EDA tool write access time and retention time, average power dissipation.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1339376

References:

[1] X. Liang, R. Canal, G.-Y. Wei, and D. Brooks, “Process variation tolerant 3t1d-based cache architectures,” in Proc. International Symposium on Microarchitecture (MICRO-40), Dec 2007.
[2] A. Agarwal, B. C. Paul, H. Mahmoodi, A. Datta, , and K. Roy, “A process-tolerant cache architecture for improved yield in nanoscale technologies,” IEEE Transactions on Very Large Scale Integration Systems, vol. 13, 2005.
[3] W. K. Luk, J. Cai, R. H. Dennard, M. J. Immediato, and S. V.Kosonocky, “A 3-transistor dram cell with gated diode for enhanced speed and retention time,” in Proc. Symposium on VLSI Technology and Circuits, June 2006.
[4] W. Luk, R. Dennard, Gated-diode amplifiers, IEEE Transactions on, Circuits and Systems II: Express Briefs 52 (5) (2005) 266–270.
[5] International Technology Roadmap for Semiconductors- 2013Edition.
[6] K. Lovin, B. Lee, X. Liang, D. Brooks, G. Wei, Empirical performance models for 3T1D memories, in: IEEE International Conference on Computer Design, 2009. ICCD 2009, 2010, pp. 398–403.
[7] Robert Giterman, Adam Teman, Pascal Meinerzhagen, Lior Atias, Andreas Burg, and Alexander Fish “Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications,” IEEE Transactions on VLSI Systems, vol. 24, no. 1, january 2016.