A Case Study of Limited Dynamic Voltage Frequency Scaling in Low-Power Processors

Authors: Hwan Su Jung, Ahn Jun Gil, Jong Tae Kim

Abstract:

Power management techniques are necessary to save power in the microprocessor. By changing the frequency and/or operating voltage of processor, DVFS can control power consumption. In this paper, we perform a case study to find optimal power state transition for DVFS. We propose the equation to find the optimal ratio between executions of states while taking into account the deadline of processing time and the power state transition delay overhead. The experiment is performed on the Cortex-M4 processor, and average 6.5% power saving is observed when DVFS is applied under the deadline condition.

Keywords: Deadline, Dynamic Voltage Frequency Scaling, Power State Transition.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1129998

References:

[1] N. Min-Allah et al, “Towards Dynamic Voltage Scaling in Real-Time Systems - A Survey”, International Journal of Computer Sciences and Engineering Systems, Vol.1, No.2, 2007.
[2] W. Liang et al, “An Energy Conservation DVFS Algorithm for Android Operating System”, Journal of Convergence, 2010.
[3] M. Shalan et al, “Online Power Management using DVFS for RTOS”, Design and Test Workshop, 2009 4th International.
[4] ST life. augmented AN4635 Application note, May 2014.
[5] ST life. augmented RM0090 Reference manual, July 2015.