@article{(Open Science Index):https://publications.waset.org/pdf/10004936,
	  title     = {Analysis of Performance of 3T1D Dynamic  Random-Access Memory Cell},
	  author    = {Nawang Chhunid and  Gagnesh Kumar},
	  country	= {},
	  institution	= {},
	  abstract     = {On-chip memories consume a significant portion of the overall die space and power in modern microprocessors. On-chip caches depend on Static Random-Access Memory (SRAM) cells and scaling of technology occurring as per Moore’s law. Unfortunately, the scaling is affecting stability, performance, and leakage power which will become major problems for future SRAMs in aggressive nanoscale technologies due to increasing device mismatch and variations. 3T1D Dynamic Random-Access Memory (DRAM) cell is a non-destructive read DRAM cell with three transistors and a gated diode. In 3T1D DRAM cell gated diode (D1) acts as a storage device and also as an amplifier, which leads to fast read access. Due to its high tolerance to process variation, high density, and low cost of memory as compared to 6T SRAM cell, it is universally used by the advanced microprocessor for on chip data and program memory. In the present paper, it has been shown that 3T1D DRAM cell can perform better in terms of fast read access as compared to 6T, 4T, 3T SRAM cells, respectively.},
	    journal   = {International Journal of Electronics and Communication Engineering},
	  volume    = {10},
	  number    = {7},
	  year      = {2016},
	  pages     = {919 - 922},
	  ee        = {https://publications.waset.org/pdf/10004936},
	  url   	= {https://publications.waset.org/vol/115},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 115, 2016},
	}