Search results for: high speed clocking in electronic circuit

Authors: Somaye Abdollahi Pour, Mohsen Saneei

Abstract:

This paper describes a novel monitoring scheme to minimize total active power in digital circuits depend on the demand frequency, by adjusting automatically both supply voltage and threshold voltages based on circuit operating conditions such as temperature, process variations, and desirable frequency. The delay monitoring results, will be control and apply so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. Design details of power monitor are examined using simulation framework in 32nm BTPM model CMOS process. Experimental results show the overhead of proposed circuit in terms of its power consumption is about 40 μW for 32nm technology; moreover the results show that our proposed circuit design is not far sensitive to the temperature variations and also process variations. Besides, uses the simple blocks which offer good sensitivity, high speed, the continuously feedback loop. This design provides up to 40% reduction in power consumption in active mode.

Keywords: active mode, delay monitor, body biasing, VDD scaling, low power.

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Authors: Y. Kobori, L. Xing, H. Gao, N.Onozawa, S. Wu, S. N. Mohyar, Z. Nosker, H. Kobayashi, N. Takai, K. Niitsu

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This paper proposes two types of non-isolated direct AC-DC converters. First, it shows a buck-boost converter with an H-bridge, which requires few components (three switches, two diodes, one inductor and one capacitor) to convert AC input to DC output directly. This circuit can handle a wide range of output voltage. Second, a direct AC-DC buck converter is proposed for lower output voltage applications. This circuit is analyzed with output voltage of 12V. We describe circuit topologies, operation principles and simulation results for both circuits.

Keywords: AC-DC converter, Buck-boost converter, Buck converter, PFC, BCM PFC circuit.

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Authors: Pedro Luis Ferrer Penalver, Edmundo da Silva Braga

Abstract:

In this paper, the performance of a simple surge protection for a direct current circuit was simulated. The protection circuit was developed from modified electric macro models of a gas discharge tube and a transient voltage suppressor diode. Moreover, a combination wave generator circuit was used as source of energy surges. The simulations showed that the circuit presented ensures immunity corresponding with test level IV of the IEC 61000-4-5:2014 international standard. The developed circuit can be modified to meet the requirements of any other equipment to be protected. Similarly, the parameters of the combination wave generator can be changed to provide different surge amplitudes.

Keywords: Combination wave generator, IEC 61000-4-5, Pspice simulation, surge protection.

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Authors: Jung-Ho Moon, Tae Kwon Ha

Abstract:

In the present study, M2 high speed steels were fabricated by using electro-slag rapid remelting process. Carbide structure was analysed and the fracture toughness and hardness were also measured after austenitization treatment at 1190 and 1210oC followed by tempering treatment at 535oC for billets with various diameters from 16 to 60 mm. Electro-slag rapid remelting (ESRR) process is an advanced ESR process combined by continuous casting and successfully employed in this study to fabricate a sound M2 high speed ingot. Three other kinds of commercial M2 high speed steels, produced by traditional method, were also analysed for comparison. Distribution and structure of eutectic carbides of the ESRR billet were found to be comparable to those of commercial alloy and so was the fracture toughness.

Keywords: High speed tool steel, eutectic carbide, microstructure, hardness, fracture toughness.

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Authors: Ali A. Mehna, Mohmed A. Ali, Ali S. Zayed

Abstract:

A numbers of important developments have led to an increasing attractiveness for very high speed electrical machines (either motor or generator). Specifically the increasing switching speed of power electronics, high energy magnets, high strength retaining materials, better high speed bearings and improvements in design analysis are the primary drivers in a move to higher speed. The design challenges come in the mechanical design both in terms of strength and resonant modes and in the electromagnetic design particularly in respect of iron losses and ac losses in the various conducting parts including the rotor. This paper describes detailed design work which has been done on a 50,000 rpm, 50kW permanent magnet( PM) synchronous machine. It describes work on electromagnetic and rotor eddy current losses using a variety of methods including both 2D finite element analysis

Keywords: High speed, PM motor, rotor and stator losses, finiteelement analysis

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Authors: Shengqi Yu, Jinwei Zhao

Abstract:

This paper presents a kind of analog circuit based temperature control system, which is mainly composed by threshold control signal circuit, synchronization signal circuit and trigger pulse circuit. Firstly, the temperature feedback signal function is realized by temperature sensor TS503F3950E. Secondly, the main control circuit forms the cycle controlled pulse signal to control the thyristor switching model. Finally two reverse paralleled thyristors regulate the output power by their switching state. In the consequence, this is a modernized and energy-saving domestic electric heating system.

Keywords: Time base circuit, automatic control, zero-crossing trigger, temperature control.

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Authors: Kritphon Phanruttanachai, Winai Jaikla

Abstract:

This article presents a current-mode quadrature oscillator using differential different current conveyor (DDCC) and voltage differencing transconductance amplifier (VDTA) as active elements. The proposed circuit is realized fro m a non-inverting lossless integrator and an inverting second order low-pass filter. The oscillation condition and oscillation frequency can be electronically/orthogonally controlled via input bias currents. The circuit description is very simple, consisting of merely 1 DDCC, 1 VDTA, 1 grounded resistor and 3 grounded capacitors. Using only grounded elements, the proposed circuit is then suitable for IC architecture. The proposed oscillator has high output impedance which is easy to cascade or dive the external load without the buffer devices. The PSPICE simulation results are depicted, and the given results agree well with the theoretical anticipation. The power consumption is approximately 1.76mW at ±1.25V supply voltages.

Keywords: Current-mode, oscillator, integrated circuit, DDCC, VDTA

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Authors: Igor Luiz Bernardes de Moura, Luan Carlos de Sena Monteiro Ozelim, Fabiano Araujo Soares

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The development of an low cost acquisition system of S-EMG signals which are reliable, comfortable for the user and with high mobility shows to be a relevant proposition in modern biomedical engineering scenario. In the study, the sampling capacity of the Arduino microcontroller Atmel Atmega328 with an A / D converter with 10-bit resolution and its reconstructing capability of a signal of surface electromyography is analyzed. An electronic circuit to capture the signal through two differential channels was designed, signals from Biceps Brachialis of a healthy man of 21 years was acquired to test the system prototype. ARV, MDF, MNF and RMS estimators were used to compare de acquired signals with physiological values. The Arduino was configured with a sampling frequency of 1.5kHz for each channel, and the tests with the circuit designed offered a SNR of 20.57dB.

Keywords: Eletromyography, Arduino, Low-Cost, Atmel Atmega328 microcontroller.

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Authors: Yngvar Berg, Omid Mirmotahari

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In this paper we ultra low-voltage and high speed CMOS domino logic. For supply voltages below 500mV the delay for a ultra low-voltage NAND2 gate is aproximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch is much less than for conventional CMOS. Differential domino gates for AND/NAND and OR/NOR operation are presented.

Keywords: Low-voltage, high-speed, NAND, NOR, CMOS.

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Authors: Santanu Santra, Utpal Roy

Abstract:

Quantum-dot Cellular Automata (QCA) is one of the most substitute emerging nanotechnologies for electronic circuits, because of lower power consumption, higher speed and smaller size in comparison with CMOS technology. The basic devices, a Quantum-dot cell can be used to implement logic gates and wires. As it is the fundamental building block on nanotechnology circuits. By applying XOR gate the hardware requirements for a QCA circuit can be decrease and circuits can be simpler in terms of level, delay and cell count. This article present a modest approach for implementing novel optimized XOR gate, which can be applied to design many variants of complex QCA circuits. Proposed XOR gate is simple in structure and powerful in terms of implementing any digital circuits. In order to verify the functionality of the proposed design some complex implementation of parity generator and parity checker circuits are proposed and simulating by QCA Designer tool and compare with some most recent design. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.

Keywords: Clock, CMOS technology, Logic gates, QCA Designer, Quantum-dot Cellular Automata (QCA).

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Authors: M. Jalali Azizpour, H. Mohammadi majd

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In this paper, the wear of high speed steel hobs during hobbing has been studied. The wear mechanisms are strongly influenced by the choice of cutting speed. At moderate and high cutting speeds three major wear mechanisms were identified: abrasion, mild adhesive and severe adhesive. The microstructure and wear behavior of two high speed steel grades (M2 and ASP30) has been compared. In contrast, a variation in chemical composition or microstructure of HSS tool material generally did not change the dominant wear mechanism. However, the tool material properties determine the resistance against the operating wear mechanism and consequently the tool life. The metallographic analysis and wear measurement at the tip of hob teeth included scanning electron microscopy and stereoscope microscopy. Roughness profilometery is used for measuring the gear surface roughness.

Keywords: abrasion, adhesion, cutting speed, hobbing, wear mechanism

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Authors: Jin-Ho Bae, Yong-Tae Kim, S K Deb Nath, Seo-Ik Kang, Sung-Gaun Kim

Abstract:

Reno-pin contact test is a method that is controlled by DC motor used to characterize electronic chips. This method is used in electronic and telecommunication devices. A new electric performance testing system is developed in which the testing method is controlled by using Piezoelectric Transducer (PZT) instead of DC motor which reduces vibration and noise. The vertical displacement of the Reno-pin is very short in the Reno-pin contact testing system. Now using a flexible guide in the new Reno-pin contact system, the vertical movement of the Reno-pin is increased many times of the existing Reno-pin contact testing method using DC motor. Using the present electric performance testing system with a flexible hinge and PZT instead of DC motor, manufacturing of electronic chips are able to characterize chips with low cost and high speed.

Keywords: PZT Actuator, Chip test, Mechanical amplifier

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Authors: Jean-Michel Sahut

Abstract:

Despite the strong and consistent increase in the use of electronic payment methods worldwide, the diffusion of electronic wallets is still far from widespread. Analysis of the failure of electronic wallet uptake has either focused on technical issues or chosen to analyse a specific scheme. This article proposes a joint approach to analysing key factors affecting the adoption of e-wallets by using the ‘Technology Acceptance Model” [1] which we have expanded to take into account the cost of using e-wallets. We use this model to analyse Monéo, the only French electronic wallet still in operation.

Keywords: Electronic wallet, adoption, ICT, TAM, Monéo, electronic payment.

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Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar

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Fast delay estimation methods, as opposed to simulation techniques, are needed for incremental performance driven layout synthesis. On-chip inductive effects are becoming predominant in deep submicron interconnects due to increasing clock speed and circuit complexity. Inductance causes noise in signal waveforms, which can adversely affect the performance of the circuit and signal integrity. Several approaches have been put forward which consider the inductance for on-chip interconnect modelling. But for even much higher frequency, of the order of few GHz, the shunt dielectric lossy component has become comparable to that of other electrical parameters for high speed VLSI design. In order to cope up with this effect, on-chip interconnect has to be modelled as distributed RLCG line. Elmore delay based methods, although efficient, cannot accurately estimate the delay for RLCG interconnect line. In this paper, an accurate analytical delay model has been derived, based on first and second moments of RLCG interconnection lines. The proposed model considers both the effect of inductance and conductance matrices. We have performed the simulation in 0.18μm technology node and an error of as low as less as 5% has been achieved with the proposed model when compared to SPICE. The importance of the conductance matrices in interconnect modelling has also been discussed and it is shown that if G is neglected for interconnect line modelling, then it will result an delay error of as high as 6% when compared to SPICE.

Keywords: Delay Modelling; On-Chip Interconnect; RLCGInterconnect; Ramp Input; Damping; VLSI

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Authors: Ambuj Kumar, Sunil Kumar Singh, Shrikant Singh

Abstract:

Sweep frequency response analysis has been turning out a powerful tool for investigation of mechanical as well as electrical integration of transformers. In this paper various aspect of practical application of SFRA has been studied. Open circuit and short circuit measurement were done on different phases of high voltage and low voltage winding. A case study was presented for the transformer of rating 31.5 MVA for various frequency ranges. A clear picture was presented for sub- frequency ranges for HV as well as LV winding. The main motive of work is to investigate high voltage short circuit response. The theoretical concept about SFRA responses is validated with expert system software results.

Keywords: Frequency deviation, OCT & SCT, SFRA, Transformer winding.

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Authors: Yogesh Pahariya, Rakesh Saxena, Biswaroop Sarkar

Abstract:

The selection of control strategy depends on the converters of the drive including power, speed, performance and the possible system costs. A number of attempts were therefore made in recent times to develop novel power electronic converter structures for SRM drives, based on the utilization. Many of the converters with variable speed drives have no input power factor correction circuits. This results in harmonic pollution of the utility supply, which should be avoided. The effect of power factor variation in terms of harmonic content is also analyzed in this study. The proposed topologies were simulated using MATLAB / Simulink software package and the results are obtained.

Keywords: Harmonic Pollution, Power Electronic Converter, Power Quality, Simulation.

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Authors: Davit Mirzoyan, Ararat Khachatryan

Abstract:

A process corner monitoring circuit (PCMC) is presented in this work. The circuit generates a signal, the logical value of which depends on the process corner only. The signal can be used in both digital and analog circuits for testing and compensation of process variations (PV). The presented circuit uses only metal-oxide-semiconductor (MOS) transistors, which allow increasing its detection accuracy, decrease power consumption and area. Due to its simplicity the presented circuit can be easily modified to monitor parametrical variations of only n-type and p-type MOS (NMOS and PMOS, respectively) transistors, resistors, as well as their combinations. Post-layout simulation results prove correct functionality of the proposed circuit, i.e. ability to monitor the process corner (equivalently die-to-die variations) even in the presence of within-die variations.

Keywords: Detection, monitoring, process corner, process variation.

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Authors: Chih Chin Yang, Chung Shan Sun

Abstract:

In this paper the relationships between professional competences and school curriculain IC design industry are explored. The semi-structured questionnaire survey and focus group interview is the research method. Study participants are graduates of microelectronics engineering professional departments who are currently employed in the IC industry. The IC industries are defined as the electronic component manufacturing industry and optical-electronic component manufacturing industry in the semiconductor industry and optical-electronic material devices, respectively. Study participants selected from IC design industry include IC engineering and electronic & semiconductor engineering. The human training with IC design professional competence in microelectronics engineering professional departments is explored in this research. IC professional competences of human resources in the IC design industry include general intelligence and professional intelligence.

Keywords: IC design, curricula, competence, task, duty.

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Authors: Jae Hyung Noh, Hang Geun Jeong

Abstract:

The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discharging current causes phase offset and reference spurs in a PLL. We propose a new charge-pump circuit to reduce the current mismatch by using a regulated cascode circuit. The proposed charge-pump circuit is designed and simulated by spectre with TSMC 0.18-μm 1.8-V CMOS technology.

Keywords: Phase-locked loop (PLL), charge-pump, phase/frequency detector (PFD), regulated cascode.

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Authors: P. Silapan, C. Chanapromma, T. Worachak

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This article proposes a current-mode square-rooting circuit using current follower transconductance amplifier (CTFA). The amplitude of the output current can be electronically controlled via input bias current with wide input dynamic range. The proposed circuit consists of only single CFTA. Without any matching conditions and external passive elements, the circuit is then appropriate for an IC architecture. The magnitude of the output signal is temperature-insensitive. The PSpice simulation results are depicted, and the given results agree well with the theoretical anticipation. The power consumption is approximately 1.96mW at ±1.5V supply voltages.

Keywords: CFTA, Current-mode, Square-rooting Circuit

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Authors: Moorthi S., Meganathan D., Janarthanan D., Praveen Kumar P., J. Raja paul perinbam

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An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps at 100MHz. Since the digitally controlled oscillator (DCO) can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for System-on-Chip (SoC) applications.

Keywords: All Digital Phase Locked Loop (ADPLL), Systemon-Chip (SoC), Phase Locked Loop (PLL), Very High speedIntegrated Circuit (VHSIC) Hardware Description Language(VHDL), Digitally Controlled Oscillator (DCO), Phase frequencydetector (PFD) and Voltage Controlled Oscillator (VCO).

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Authors: Shipra Upadhyay , R. K. Nagaria, R. A. Mishra

Abstract:

In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adder circuit exhibits the energy saving of 70% to the conventional CMOS full adder circuit, at 100 MHz frequency and 1.8V operating voltage.

Keywords: Adiabatic, CEPAL, full adder, power clock

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Authors: Rafik Medjoudj, Rabah Medjoudj, D. Aissani

Abstract:

The electrical substation components are often subject to degradation due to over-voltage or over-current, caused by a short circuit or a lightning. A particular interest is given to the circuit breaker, regarding the importance of its function and its dangerous failure. This component degrades gradually due to the use, and it is also subject to the shock process resulted from the stress of isolating the fault when a short circuit occurs in the system. In this paper, based on failure mechanisms developments, the wear out of the circuit breaker contacts is modeled. The aim of this work is to evaluate its reliability and consequently its residual lifetime. The shock process is based on two random variables such as: the arrival of shocks and their magnitudes. The arrival of shocks was modeled using homogeneous Poisson process (HPP). By simulation, the dates of short-circuit arrivals were generated accompanied with their magnitudes. The same principle of simulation is applied to the amount of cumulative wear out contacts. The objective reached is to find the formulation of the wear function depending on the number of solicitations of the circuit breaker.

Keywords: reliability, short-circuit, models of shocks.

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Authors: L. Tani, N. El Ouzzani

Abstract:

Crosstalk among interconnects and printed-circuit board (PCB) traces is a major limiting factor of signal quality in highspeed digital and communication equipments especially when fast data buses are involved. Such a bus is considered as a planar multiconductor transmission line. This paper will demonstrate how the finite difference time domain (FDTD) method provides an exact solution of the transmission-line equations to analyze the near end and the far end crosstalk. In addition, this study makes it possible to analyze the rise time effect on the near and far end voltages of the victim conductor. The paper also discusses a statistical analysis, based upon a set of several simulations. Such analysis leads to a better understanding of the phenomenon and yields useful information.

Keywords: Multiconductor transmission line, Crosstalk, Finite difference time domain (FDTD), printed-circuit board (PCB), Rise time, Statistical analysis.

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Authors: Z. Feng, V. Viswanathan, D. Navarro, I. O'Connor

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This paper presents a new high speed simulation methodology to solve the long simulation time problem of CMOS image sensor matrix. Generally, for integrating the pixel matrix in SOC and simulating the system performance, designers try to model the pixel in various modeling languages such as VHDL-AMS, SystemC or Matlab. We introduce a new alternative method based on spice model in cadence design platform to achieve accuracy and reduce simulation time. The simulation results indicate that the pixel output voltage maximum error is at 0.7812% and time consumption reduces from 2.2 days to 13 minutes achieving about 240X speed-up for the 256x256 pixel matrix.

Keywords: CMOS image sensor, high speed simulation, image sensor matrix simulation.

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Authors: T. Vigneswaran, B. Mukundhan, P. Subbarami Reddy

Abstract:

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.

Keywords: Arithmetic circuit, full adder, multiplier, low power, very Large-scale integration (VLSI).

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Authors: H. A. Majid, N. Razali, M. S. Sulaiman, A. K. A'ain

Abstract:

A new interface circuit for capacitive sensor is presented. This paper presents the design and simulation of soil moisture capacitive sensor interface circuit based on phase differential technique. The circuit has been designed and fabricated using MIMOS- 0.35"m CMOS technology. Simulation and test results show linear characteristic from 36 – 52 degree phase difference, representing 0 – 100% in soil moisture level. Test result shows the circuit has sensitivity of 0.79mV/0.10 phase difference, translating into resolution of 10% soil moisture level.

Keywords: Capacitive sensor, interface, phase differential.

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Authors: Jason Chien-Hsun Tseng, Nguyen Dong-Thai Dao, Chong-Ching Chang

Abstract:

A novel PDE solver using the multidimensional wave digital filtering (MDWDF) technique to achieve the solution of a 2D seismic wave system is presented. In essence, the continuous physical system served by a linear Kirchhoff circuit is transformed to an equivalent discrete dynamic system implemented by a MD wave digital filtering (MDWDF) circuit. This amounts to numerically approximating the differential equations used to describe elements of a MD passive electronic circuit by a grid-based difference equations implemented by the so-called state quantities within the passive MDWDF circuit. So the digital model can track the wave field on a dense 3D grid of points. Details about how to transform the continuous system into a desired discrete passive system are addressed. In addition, initial and boundary conditions are properly embedded into the MDWDF circuit in terms of state quantities. Graphic results have clearly demonstrated some physical effects of seismic wave (P-wave and S–wave) propagation including radiation, reflection, and refraction from and across the hard boundaries. Comparison between the MDWDF technique and the finite difference time domain (FDTD) approach is also made in terms of the computational efficiency.

Keywords: Seismic Wave Propagation, Multi-dimension WaveDigital Filters, Partial Differential Equations.

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Authors: Ming-Ta Yang, Jyh-Cherng Gu, Chun-Wei Huang, Jin-Lung Guan

Abstract:

Time base maintenance (TBM) is conventionally applied by the power utilities to maintain circuit breakers (CBs), transformers, bus bars and cables, which may result in under maintenance or over maintenance. As information and communication technology (ICT) industry develops, the maintenance policies of many power utilities have gradually changed from TBM to condition base maintenance (CBM) to improve system operating efficiency, operation cost and power supply reliability. This paper discusses the feasibility of using intelligent electronic devices (IEDs) to construct a CB CBM management platform. CBs in power substations can be monitored using IEDs with additional logic configuration and wire connections. The CB monitoring data can be sent through intranet to a control center and be analyzed and integrated by the Elipse Power Studio software. Finally, a human-machine interface (HMI) of supervisory control and data acquisition (SCADA) system can be designed to construct a CBM management platform to provide maintenance decision information for the maintenance personnel, management personnel and CB manufacturers.

Keywords: Circuit breaker, Condition base maintenance, Intelligent electronic device, Time base maintenance, SCADA.

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Authors: Romain Bosquet, Pierre-Olivier Vandanjon, Alex Coiret, Tristan Lorino

Abstract:

In the hardening energy context, the transport sector which constitutes a large worldwide energy demand has to be improving for decrease energy demand and global warming impacts. In a controversial situation where subsists an increasing demand for long-distance and high-speed travels, high-speed trains offer many advantages, as consuming significantly less energy than road or air transports. At the project phase of new rail infrastructures, it is nowadays important to characterize accurately the energy that will be induced by its operation phase, in addition to other more classical criteria as construction costs and travel time. Current literature consumption models used to estimate railways operation phase are obsolete or not enough accurate for taking into account the newest train or railways technologies. In this paper, an updated model of consumption for high-speed is proposed, based on experimental data obtained from full-scale tests performed on a new high-speed line. The assessment of the model is achieved by identifying train parameters and measured power consumptions for more than one hundred train routes. Perspectives are then discussed to use this updated model for accurately assess the energy impact of future railway infrastructures.

Keywords: High-speed train, energy, model, track profile, infrastructure

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