Search results for: Meganathan D.

3 Simulink Model of Reference Frame Theory Based Three Phase Shunt Active Filter

Authors: P. Nammalvar, P. Meganathan, A. Balamuguran

Abstract:

Among various active filters, shunt active filter is a viable solution for reactive power and harmonics compensation. In this paper, the SRF plan is used to generate current reference for compensation and conventional PI controllers were used as the controller to compensate the reactive power. The design of the closed loop controllers is reserved simple by modeling them as first order systems. Computationally uncomplicated and efficient SVM system is used in the present work for better utilization of dc bus voltage. The rating of shunt active filter has been finalized based on the reactive power demand of the selected reactive load. The proposed control and SVM technique are validated by simulating in MATLAB software.

Keywords: Shunt Active Filter, Space vector pulse width modulation, Voltage Source Converter, Reactive Power, Synchronous Reference Frame, Point of common coupling.

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2 A Novel Three Phase Hybrid Unidirectional Rectifier for High Power Factor Applications

Authors: P. Nammalvar, P. Meganathan

Abstract:

This paper presents a hybrid three phase rectifier for high power factor application. This rectifier is composed by zero voltage transition (ZVT) and zero current transition (ZCT) boost converter with three phase diode bridge rectifier, in parallel with a six pulse three phase pulse width modulation (PWM) controlled rectifier. The proposed topology is capable of high power factor with DC output voltage regulation by providing sinusoidal input. Also, it increases the overall efficiency of the new hybrid rectifier to 94.56% and the total harmonic distortion of the hybrid structure varies from 0% to 16% at nominal output power. This topology was simulated in MATLAB/SIMULINK environment and the output waveforms presented with experimental result.

Keywords: Hybrid Rectifier, Total Harmonic Distortion, Power Quality, Pulse Width Modulation (PWM), Unidirectional Rectifier.

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1 Low Jitter ADPLL based Clock Generator for High Speed SoC Applications

Authors: Moorthi S., Meganathan D., Janarthanan D., Praveen Kumar P., J. Raja paul perinbam

Abstract:

An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps at 100MHz. Since the digitally controlled oscillator (DCO) can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for System-on-Chip (SoC) applications.

Keywords: All Digital Phase Locked Loop (ADPLL), Systemon-Chip (SoC), Phase Locked Loop (PLL), Very High speedIntegrated Circuit (VHSIC) Hardware Description Language(VHDL), Digitally Controlled Oscillator (DCO), Phase frequencydetector (PFD) and Voltage Controlled Oscillator (VCO).

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