Design and Optimization of Parity Generator and Parity Checker Based On Quantum-dot Cellular Automata

Authors: Santanu Santra, Utpal Roy

Abstract:

Quantum-dot Cellular Automata (QCA) is one of the most substitute emerging nanotechnologies for electronic circuits, because of lower power consumption, higher speed and smaller size in comparison with CMOS technology. The basic devices, a Quantum-dot cell can be used to implement logic gates and wires. As it is the fundamental building block on nanotechnology circuits. By applying XOR gate the hardware requirements for a QCA circuit can be decrease and circuits can be simpler in terms of level, delay and cell count. This article present a modest approach for implementing novel optimized XOR gate, which can be applied to design many variants of complex QCA circuits. Proposed XOR gate is simple in structure and powerful in terms of implementing any digital circuits. In order to verify the functionality of the proposed design some complex implementation of parity generator and parity checker circuits are proposed and simulating by QCA Designer tool and compare with some most recent design. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.

Keywords: Clock, CMOS technology, Logic gates, QCA Designer, Quantum-dot Cellular Automata (QCA).

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1091768

References:

[1] R. Compano, L. Molenkamp, and D.J. Paul, European Commission IST Programme,FET Conf., 1999.
[2] S.Timarchi,K.Navi, IEEE Trans. On Instrumentation and Measurement, Vol. 58 Issue:9, pp. 2959-2968 2009. doi:10.1109/TIM.2009.2016793.
[3] A.O.Orlov,I.Amlani,G.H.Bernstein,C.S.Lent,G.L.Snider,Science Vol. 277 no. 5328 pp. 928-930, 1997.
[4] P.Tougaw,C.Lent, Journal of Applied Physics vol.75 no.3 pp. 1818 – 1825. 1994.
[5] C. Lent, P. Tougaw, W. Porod, and G. Bernstein,, Nanotechnology vol. 4 pp. 49-57, 1993.
[6] J D JacksonJhon Wiley and Sons, 1999.
[7] J. Huang, M. Momenzadeh, M. Ottavi, L. Schiano, F. Lombardi,Internal report, (2004).
[8] M. Momenzadeh, J. Huang, M. Ottavi, N. Park, F. Lombardi,Internal report, (2004).
[9] J. Timler and C.S. Lent, Journal of Applied Physics, vol. 91, pp. 823-831, (2002).
[10] C. S. Lent, P. D. Tougaw and W. Porod, Proc. of the Workshop on Physics and Computing, pp. 5–13, (1994).
[11] C. G. Smith, Science, vol. 284, 274, (1999).
[12] S. Santra, U. Roy,International Journal of Computer, Information Science and Engineering , WASET,Vol:8 No:1, PP 168-173 (2014)
[13] C. S. Lent and P. D. Tougaw, Proc. IEEE, vol. 85, no. 4, pp. 541–557, Apr. (1997).
[14] K. Hennessy and C. S. Lent, J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 19, no. 5, pp. 1752–1755, Sep. (2001).
[15] D. A. Antonelli, D. Z. Chen, T. J. Dysart, X. S. Hu, A. B. Kahng, P. M. Kogge, R. C. Murphy and M. T. Niemier, Design Automation Conference (DAC), pp. 363–368, (2004).
[16] K. Walus, G. A. Jullien and V. S. Dimitrov, Proceedings of Asimolar Conference, (2003).
[17] M. Mustafa, M R Beigh, Indian Journal of Pure & Applied Physics, vol. 51 pp.60-66,(2013).
[18] M.R.Beigh,M.Mustafa,F. Ahmad, Circuits and Systems vol.4 pp. 147-156 (2013).
[19] K. Walus, T. Dysart, G. Jullien, and R. Budiman, IEEE Trans. Nanotechnol., vol. 3, no. 1, pp. 2629, Mar. 2004.
[20] Kyosun Kim, Kaijie Wu, and Ramesh Karri, IEEE transactions on computer-aided design of integrated circuits and systems, vol. 26, no. 1, January 2007.
[21] W Wang, K Walus, G AJullien, In proceedings of IEEE Conference on Nanotechnology, PP 461-464, 2003.
[22] H.S. Jagarlamudi, M Saha, PK Jagarlamudi, World Academy of Science, Engineering and Technology, Vol. 60 PP 486-490 2011.
[23] Vishnu T C, Polisetti&Santosh K, 3rd Annual IEEE-International conference on Nano/Micro Engineered Molecular Systems, China (2008).
[24] M Mustafa, M R Beigh, Indian Journal of Pure & Applied Physics, Vol. 51, PP 60-66 (2013).
[25] V.C. Teja, S. Poliseti, S. Kasavajjala, 3rd IEEE Int. Conf. on Nano/Micro Engineered and Molecular Systems, PP 758-763 (2008).