Search results for: All Digital Phase Locked Loop (ADPLL)

Authors: Moorthi S., Meganathan D., Janarthanan D., Praveen Kumar P., J. Raja paul perinbam

Abstract:

An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps at 100MHz. Since the digitally controlled oscillator (DCO) can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for System-on-Chip (SoC) applications.

Keywords: All Digital Phase Locked Loop (ADPLL), Systemon-Chip (SoC), Phase Locked Loop (PLL), Very High speedIntegrated Circuit (VHSIC) Hardware Description Language(VHDL), Digitally Controlled Oscillator (DCO), Phase frequencydetector (PFD) and Voltage Controlled Oscillator (VCO).

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Authors: Jiri Sebesta

Abstract:

Phase locked loops (PLL) and delay locked loops (DLL) play an important role in establishing coherent references (phase of carrier and symbol timing) in digital communication systems. Fully digital receiver including digital carrier synchronizer and symbol timing synchronizer fulfils the conditions for universal multi-mode communication receiver with option of symbol rate setting over several digit places and long-term stability of requirement parameters. Afterwards it is necessary to realize PLL and DLL in synchronizer in digital form and to approach to these subsystems as a discrete representation of analog template. Analysis of discrete phase locked loop (DPLL) or discrete delay locked loop (DDLL) and technique to determine their characteristics based on analog (continuous-time) template is performed in this posed paper. There are derived transmission response and error function for 1st order discrete locked loop and resulting equations and graphical representations for 2nd order one. It is shown that the spectrum translation due to sampling takes effect at frequency characteristics computing for specific values of loop parameters.

Keywords: Carrier synchronization, coherent demodulation, software defined receiver, symbol timing.

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Authors: Benmabrouk. Zaineb, Ben Hamed. Mouna, Lassad. Sbita

Abstract:

This article deals to describe the simulation investigation of the digital phase locked loop implemented in software (SDPLL). SDPLL has been developed for speed drives of an induction motor in scalar strategy. A drive was implemented and simulation results are presented to verify the robustness against motor parameter variation and regulation speed.

Keywords: Induction motor, Software Digital Phase LockedLoop, Speed control, Simulation.

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Authors: Naima Ikken, Abdelhadi Bouknadel, Nour-eddine Tariba Ahmed Haddou, Hafsa El Omari

Abstract:

The operation of grid-connected inverters necessity a single-phase phase locked loop (PLL) is proposed in this article to accurately and quickly estimate and detect the grid phase angle. This article presents the improvement of a method of phase-locked loop. The novelty is to generate a method (PLL) of synchronizing the grid with a Notch filter based on adaptive fuzzy logic for inverter systems connected to the grid. The performance of the proposed method was tested under normal and abnormal operating conditions (amplitude, frequency and phase shift variations). In addition, simulation results with ISPM software are developed to verify the effectiveness of the proposed method strategy. Finally, the experimental test will be used to extract the result and discuss the validity of the proposed algorithm.

Keywords: Phase locked loop, PLL, notch filter, fuzzy logic control.

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Authors: Ahmed El Oualkadi, Abdellah Ait Ouahman

Abstract:

This paper discusses a systematic design of a Σ-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models for wireless applications in the frequency range around 2.45 GHz.

Keywords: Phase-locked loop, frequency synthesizer, fractional-N PLL, Σ-Δ modulator, HDL models

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Authors: Jae Hyung Noh, Hang Geun Jeong

Abstract:

The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discharging current causes phase offset and reference spurs in a PLL. We propose a new charge-pump circuit to reduce the current mismatch by using a regulated cascode circuit. The proposed charge-pump circuit is designed and simulated by spectre with TSMC 0.18-μm 1.8-V CMOS technology.

Keywords: Phase-locked loop (PLL), charge-pump, phase/frequency detector (PFD), regulated cascode.

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Authors: R .H. Talwekar, S. S Limaye

Abstract:

The designing of charge pump with high gain Op- Amp is a challenging task for getting faithful response .Design of high performance phase locked loop require ,a design of high performance charge pump .We have designed a operational amplifier for reducing the error caused by high speed glitch in a transistor and mismatch currents . A separate Op-Amp has designed in 180 nm CMOS technology by CADENCE VIRTUOSO tool. This paper describes the design of high performance charge pump for GHz CMOS PLL targeting orthogonal frequency division multiplexing (OFDM) application. A high speed low power consumption Op-Amp with more than 500 MHz bandwidth has designed for increasing the speed of charge pump in Phase locked loop.

Keywords: Charge pump (CP) Orthogonal frequency divisionmultiplexing (OFDM), Phase locked loop (PLL), Phase frequencydetector (PFD), Voltage controlled oscillator (VCO),

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Authors: Irtaza M. Syed, Kaamran Raahemifar

Abstract:

This paper presents a model predictive control (MPC) of a utility interactive (UI) single phase inverter (SPI) for a photovoltaic (PV) system at residential/distribution level. The proposed model uses single-phase phase locked loop (PLL) to synchronize SPI with the grid and performs MPC control in a dq reference frame. SPI model consists of boost converter (BC), maximum power point tracking (MPPT) control, and a full bridge (FB) voltage source inverter (VSI). No PI regulators to tune and carrier and modulating waves are required to produce switching sequence. Instead, the operational model of VSI is used to synthesize sinusoidal current and track the reference. Model is validated using a three kW PV system at the input of UI-SPI in Matlab/Simulink. Implementation and results demonstrate simplicity and accuracy, as well as reliability of the model.

Keywords: Matlab/Simulink, Model Predictive Control, Phase Locked Loop, Single Phase Inverter, Voltage Source Inverter.

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Authors: Ki-Jin Kim, Sanghoon Park, K. H. Ahn

Abstract:

This paper presents the 20-GHz fractional PLL (Phase Locked Loop) circuit for the next generation Wi-Fi by using 90 nm TSMC process. The newly suggested millimeter wave 16/17 pre-scalar is designed and verified by measurement to make the fractional PLL having a low quantization noise. The operational bandwidth of the 60 GHz system is 15 % of the carrier frequency which requires large value of Kv (VCO control gain) resulting in degradation of phase noise. To solve this problem, this paper adopts AFC (Automatic Frequency Controller) controlled 4-bit millimeter wave VCO with small value of Kv. Also constant Kv is implemented using 4-bit varactor bank. The measured operational bandwidth is 18.2 ~ 23.2 GHz which is 25 % of the carrier frequency. The phase noise of -58 and -96.2 dBc/Hz at 100 KHz and 1 MHz offset is measured respectively. The total power consumption of the PLL is only 30 mW.

Keywords: Millimeter Wave Fractional PLL, Wide band VCO, WPAN Transceiver.

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Authors: Syed Javed Arif, Mohd Ayyub Khan, Saleem Anwar Khan

Abstract:

In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.

Keywords: Frequency measurement, digital control, phase locked loop, encoding, Verilog HDL.

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Authors: Ararat Khachatryan, Davit Mirzoyan

Abstract:

In sub micrometer technology, the aging phenomenon starts to have a significant impact on the reliability of integrated circuits by bringing performance degradation. For that reason, it is important to have a capability to evaluate the aging effects accurately. This paper presents an accurate aging measurement approach based on phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuit. The architecture is rejecting the circuit self-aging effect from the characteristics of PLL, which is generating the frequency without any aging phenomena affects. The aging monitor is implemented in low power 32 nm CMOS technology, and occupies a pretty small area. Aging simulation results show that the proposed aging measurement circuit improves accuracy by about 2.8% at high temperature and 19.6% at high voltage.

Keywords: Nanoscale, aging, effect, NBTI, HCI.

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Authors: Nagulapati Kiran, V. Rangavalli, B. Vanajakshi

Abstract:

This paper designs the four-phase Boost Converter which overcomes the problem of high input ripple current and output ripple voltage. Digital control is more convenient for such a topology on basis of synchronization, phase shift operation, etc. Simulation results are presented for open-loop and closed-loop for four phase boost converter. This control scheme is applicable for PFC rectifiers as well. Thus a comparative analysis based on the obtained results is performed.

Keywords: Boost Converter, Bode plot, PI Controller, Four phase.

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Authors: Consalva J. Msigwa, Beda J. Kundy, Bakari M. M. Mwinyiwiwa,

Abstract:

This paper presents a method for obtaining the desired reference current for Voltage Source Converter (VSC) of the Shunt Active Power Filter (SAPF) using Synchronous Reference Frame Theory. The method relies on the performance of the Proportional-Integral (PI) controller for obtaining the best control performance of the SAPF. To improve the performance of the PI controller, the feedback path to the integral term is introduced to compensate the winding up phenomenon due to integrator. Using Reference Frame Transformation, reference signals are transformed from a - b - c stationery frame to 0 - d - q rotating frame. Using the PI controller, the reference signals in the 0 - d - q rotating frame are controlled to get the desired reference signals for the Pulse Width Modulation. The synchronizer, the Phase Locked Loop (PLL) with PI filter is used for synchronization, with much emphasis on minimizing delays. The system performance is examined with Shunt Active Power Filter simulation model.

Keywords: Phase Locked Loop (PLL), Voltage Source Converter (VSC), Shunt Active Power Filter (SAPF), PI, Pulse Width Modulation (PWM)

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Authors: Nasir Mehmood, Saad Rahman, Vinodh Ravinath, Mahesh Balaji

Abstract:

This paper describes the design of a programmable FSK-modulator based on VCO and its implementation in 0.35m CMOS process. The circuit is used to transmit digital data at 100Kbps rate in the frequency range of 400-600MHz. The design and operation of the modulator is discussed briefly. Further the characteristics of PLL, frequency synthesizer, VCO and the whole design are elaborated. The variation among the proposed and tested specifications is presented. Finally, the layout of sub-modules, pin configurations, final chip and test results are presented.

Keywords: FSK Modulator, CMOS, VCO, Phase Locked Loop, Frequency Synthesizer.

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Authors: Chen-Chien Hsu, Chun-Hui Gao

Abstract:

In this paper, a PSO-based approach is proposed to derive a digital controller for redesigned digital systems having an interval plant based on resemblance of the extremal gain/phase margins. By combining the interval plant and a controller as an interval system, extremal GM/PM associated with the loop transfer function can be obtained. The design problem is then formulated as an optimization problem of an aggregated error function revealing the deviation on the extremal GM/PM between the redesigned digital system and its continuous counterpart, and subsequently optimized by a proposed PSO to obtain an optimal set of parameters for the digital controller. Computer simulations have shown that frequency responses of the redesigned digital system having an interval plant bare a better resemblance to its continuous-time counter part by the incorporation of a PSO-derived digital controller in comparison to those obtained using existing open-loop discretization methods.

Keywords: Digital redesign, Extremal systems, Particle swarm optimization, Uncertain interval systems

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Authors: Irtaza M. Syed, Kaamran Raahemifar

Abstract:

This paper presents a model predictive control (MPC) of a utility interactive three phase inverter (TPI) for a photovoltaic (PV) system at commercial level. The proposed model uses phase locked loop (PLL) to synchronize the TPI with the power electric grid (PEG) and performs MPC control in a dq reference frame. TPI model consists of a boost converter (BC), maximum power point tracking (MPPT) control, and a three-leg voltage source inverter (VSI). The operational model of VSI is used to synthesize the sinusoidal current and track the reference. The model is validated using a 35.7 kW PV system in Matlab/Simulink. Implementation results show simplicity and accuracy, as well as reliability of the model.

Keywords: Model predictive control, three phase voltage source inverter, PV system, Matlab/Simulink.

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Authors: Jun Wang, Tingcun Wei

Abstract:

The digital pulse width modulator (DPWM) is the crucial building block for digitally-controlled DC-DC switching converter, which converts the digital duty ratio signal into its analog counterpart to control the power MOSFET transistors on or off. With the increase of switching frequency of digitally-controlled DC-DC converter, the DPWM with higher time resolution is required. In this paper, a 15-bits DPWM with three-level hybrid structure is presented; the first level is composed of a7-bits counter and a comparator, the second one is a 5-bits delay line, and the third one is a 3-bits digital dither. The presented DPWM is designed and implemented using the PLL megafunction of FPGA (Field Programmable Gate Arrays), and the required frequency of clock signal is 128 times of switching frequency. The simulation results show that, for the switching frequency of 2 MHz, a DPWM which has the time resolution of 15 ps is achieved using a maximum clock frequency of 256MHz. The designed DPWM in this paper is especially useful for high-frequency digitally-controlled DC-DC switching converters.

Keywords: DPWM, PLL megafunction, FPGA, time resolution, digitally-controlled DC-DC switching converter.

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Authors: L. Boukhris, A. Boudjemai, A. Bellar, R. Roubache, M. Bensaada

Abstract:

In space during functioning, a satellite will be heated up due to the behavior of its components such as power electronics. In order to prevent problems in the satellite, this heat has to be released in space thanks to the cooling system. This system consists of a loop heat pipe (LHP), in which a fluid streams through an evaporator and a condenser. In the evaporator, the fluid captures the heat from the satellite and evaporates. Then it flows to the condenser where it releases the heat and it condenses. In this project, the two mains parts of a cooling system are studied: the evaporator and the condenser. The study of the diphasic loop was done starting from digital simulations carried out under Matlab and Femlab.

Keywords: capillarity, condenser, evaporator, phase change, transfer of heat.

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Authors: Weiwei Shan, Wenjing Ding, Juan Ning, Chao He, Zijuan Wang

Abstract:

Gravity circulation loop for the cryopumps of the space simulator is introduced, and two phase mathematic model of flow heat transfer is analyzed as well. Based on this model, the liquid nitrogen (LN₂) gravity circulation loop including its equipment and layout is designed and has served as LN₂ feeding system for cryopumps in one large space simulator. With the help of control software and human machine interface, this system can be operated flexibly, simply, and automatically under four conditions. When running this system, the results show that the cryopumps can be cooled down and maintained under the required temperature, 120 K.

Keywords: Cryopumps, gravity circulation loop, liquid nitrogen, two-phase.

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Authors: Bilel Gassara, Mahmoud Abdellaoui, Nouri Masmoud

Abstract:

The 4G front-end transceiver needs a high performance which can be obtained mainly with an optimal architecture and a multi-band Local Oscillator. In this study, we proposed and presented a new architecture of multi-band frequency synthesizer based on an Inverse Sine Phase Detector Phase Locked Loop (ISPD PLL) without any filters and any controlled gain block and associated with adapted multi band LC tuned VCO using a several numeric controlled capacitive branches but not binary weighted. The proposed architecture, based on 0.35μm CMOS process technology, supporting Multi-band GSM/DCS/DECT/ UMTS/WiMax application and gives a good performances: a phase noise @1MHz -127dBc and a Factor Of Merit (FOM) @ 1MHz - 186dB and a wide band frequency range (from 0.83GHz to 3.5GHz), that make the proposed architecture amenable for monolithic integration and 4G multi-band application.

Keywords: GSM/DCS/DECT/UMTS/WiMax, ISPD PLL, keep and capture range, Multi-Band, Synthesizer, Wireless.

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Authors: Abdelhalim Kessal

Abstract:

This paper treats a design of combined control of a single phase power factor correction (PFC). The strategy of the proposed control is based on two parts, the first, for the outer loop (DC output regulated voltage), and the second govern the input current of the converter in order to achieve a sinusoidal form in phase with the grid voltage. Two kinds of regulators are used, Fuzzy controller for the outer loop and predictive controller for the inner loop. The controllers are verified and discussed through simulation under MATLAB/Simulink platform. Also an experimental confirmation is applied. Results present a high dynamic performance under various parameters changes.

Keywords: Boost converter, harmonic distortion, Fuzzy, prediction, unity power factor.

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Authors: Heung Sun Yoon, Jong Tae Kim

Abstract:

In this paper, we present an activity diagram model for double-loop control self-adaptive braking system. Since activity diagram helps to improve visibility of self-adaption. We can easily find where improvement is needed on double-loop control. Double-loop control is adopted since the design conditions and actual conditions can be different. The system is reconfigured in runtime by using double-loop control. We simulated to verify and validate our model by using MATLAB. We compared single-loop control model with double-loop control model. Simulation results show that double-loop control provides more consistent brake power control than single-loop control.

Keywords: Activity diagram, automotive, braking system, double-loop, Self-adaptive, UML, vehicle.

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Authors: A. Muthuramalingam, S. Himavathi

Abstract:

Harmonic pollution and low power factor in power systems caused by power converters have been of great concern. To overcome these problems several converter topologies using advanced semiconductor devices and control schemes have been proposed. This investigation is to identify a low cost, small size, efficient and reliable ac to dc converter to meet the input performance index of UPS. The performance of single phase and three phase ac to dc converter along with various control techniques are studied and compared. The half bridge converter topology with linear current control is identified as most suitable. It is simple, energy efficient because of single switch power loss and transformer-less operation of UPS. The results are validated practically using a prototype built using IGBT and analog controller. The performance for both single and three-phase system is verified. Digital implementation of closed loop control achieves higher reliability. Its cost largely depends on chosen bit precision. The minimal bit precision for optimum converter performance is identified as 16-bit with fixed-point operation. From the investigation and practical implementation it is concluded that half bridge ac – dc converter along with digital linear controller meets the performance index of UPS for single and three phase systems.

Keywords: PFC, energy efficient, half bridge, ac-dc converter, boost topology, linear current control, digital bit precision.

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Authors: Kar Foo Chong, Andreas Lee Astuti, Pradeep K. Gopalakrishnan, T. Hui Teo

Abstract:

This paper describes design of a digital feedback loop for a low switching frequency dc-dc switching converters. Low switching frequencies were selected in this design. A look up table for the digital PID (proportional integrator differentiator) compensator was implemented using Altera Stratix II with built-in ADC (analog-to-digital converter) to achieve this hardware realization. Design guidelines are given for the PID compensator, high frequency DPWM (digital pulse width modulator) and moving average filter.

Keywords: dc-dc converter, FPGA, PID, power management, .

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Authors: Mohammad Hamdan, Emad Elnajjar

Abstract:

The LHP is a two-phase device with extremely high effective thermal conductivity that utilizes the thermodynamic pressure difference to circulate a cooling fluid. A thermodynamics analytical model is developed to explore different parameters effects on a Loop Heat Pipe (LHP).. The effects of pipe length, pipe diameter, condenser temperature, and heat load are reported. As pipe length increases and/or pipe diameter decreases, a higher temperature is expected in the evaporator.

Keywords: Loop Heat Pipe, LHP, Passive Cooling, CapillaryForce.

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Authors: Hu Haibo, Liu Yi, He Ming

Abstract:

The binary phase-only filter digital watermarking embeds the phase information of the discrete Fourier transform of the image into the corresponding magnitudes for better image authentication. The paper proposed an approach of how to implement watermark embedding by quantizing the magnitude, with discussing how to regulate the quantization steps based on the frequencies of the magnitude coefficients of the embedded watermark, and how to embed the watermark at low frequency quantization. The theoretical analysis and simulation results show that algorithm flexibility, security, watermark imperceptibility and detection performance of the binary phase-only filter digital watermarking can be effectively improved with quantization based watermark embedding, and the robustness against JPEG compression will also be increased to some extent.

Keywords: binary phase-only filter, discrete Fourier transform, digital watermarking, image authentication, quantization.

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Authors: Mahdi Yaghobi, Mohammad Haeri

Abstract:

In this paper, we show that the stability can not be achieved with current stabilizing MPC methods for some unstable processes. Hence we present a new method for stabilizing these processes. The main idea is to use a new time varying weighted cost function for traditional GPC. This stabilizes the closed loop system without adding soft or hard constraint in optimization problem. By studying different examples it is shown that using the proposed method, the closed-loop stability of unstable nonminimum phase process is achieved.

Keywords: GPC, Stability, Varying Weighting Coefficients.

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Authors: Sachin Kumar, Vivek Tiwari, Goutam Dutta

Abstract:

The paper investigates parallel channel instabilities of natural circulation boiling water reactor. A thermal-hydraulic model is developed to simulate two-phase flow behavior in the natural circulation boiling water reactor (NCBWR) with the incorporation of ex-core components and recirculation loop such as steam separator, down-comer, lower-horizontal section and upper-horizontal section and then, numerical analysis is carried out for parallel channel instabilities of the reactor undergoing both in-phase and out-of-phase modes of oscillations. To analyze the relative effect on stability of the reactor due to inclusion of various ex-core components and recirculation loop, marginal stable point is obtained at a particular inlet enthalpy of the reactor core without the inclusion of ex-core components and recirculation loop and then with the inclusion of the same. Numerical simulations are also conducted to determine the relative dominance between two modes of oscillations i.e. in-phase and out-of-phase. Simulations are also carried out when the channels are subjected to asymmetric power distribution keeping the inlet enthalpy same.

Keywords: Asymmetric power distribution, Density wave oscillations, In-phase and out-of-phase modes of instabilities, Natural circulation boiling water reactor

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Authors: Tsunwai Gary Yip

Abstract:

Phase locked loops in 10 Gb/s and faster data links are low phase noise devices. Characterization of their phase jitter transfer functions is difficult because the intrinsic noise of the PLLs is comparable to the phase noise of the reference clock signal. The problem is solved by using a linear model to account for the intrinsic noise. This study also introduces a novel technique for measuring the transfer function. It involves the use of the reference clock as a source of wideband excitation, in contrast to the commonly used sinusoidal excitations at discrete frequencies. The data reported here include the intrinsic noise of a PLL for 10 Gb/s links and the jitter transfer function of a PLL for 12.8 Gb/s links. The measured transfer function suggests that the PLL responded like a second order linear system to a low noise reference clock.

Keywords: Intrinsic phase noise, jitter in data link, PLL jitter transfer function, high speed clocking in electronic circuit

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Authors: P. Bárta

Abstract:

Increasing demand on the performance of Subsea Production Systems (SPS) suggests a need for more detailed investigation of fluid behavior taking place in subsea equipment. Complete CFD cool down analyses of subsea equipment are very time demanding. The objective of this paper is to investigate a Locked CFD approach, which enables significant reduction of the computational time and at the same time maintains sufficient accuracy during thermal cool down simulations. The result comparison of a dead leg simulation using the Full CFD and the three LCFD-methods confirms the validity of the locked flow field assumption for the selected case. For the tested case the LCFD simulation speed up by factor of 200 results in the absolute thermal error of 0.5 °C (3% relative error), speed up by factor of 10 keeps the LCFD results within 0.1 °C (0.5 % relative error) comparing to the Full CFD.

Keywords: CFD, Locked Flow Field, Speed up of CFD simulation time, Subsea

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