Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 491

Search results for: Phase Locked Loop (PLL)

491 Hardware Description Language Design of Σ-Δ Fractional-N Phase-Locked Loop for Wireless Applications

Authors: Ahmed El Oualkadi, Abdellah Ait Ouahman

Abstract:

This paper discusses a systematic design of a Σ-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models for wireless applications in the frequency range around 2.45 GHz.

Keywords: Phase-locked loop, frequency synthesizer, fractional-N PLL, Σ-Δ modulator, HDL models

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490 Low Jitter ADPLL based Clock Generator for High Speed SoC Applications

Authors: Moorthi S., Meganathan D., Janarthanan D., Praveen Kumar P., J. Raja paul perinbam

Abstract:

An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps at 100MHz. Since the digitally controlled oscillator (DCO) can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for System-on-Chip (SoC) applications.

Keywords: All Digital Phase Locked Loop (ADPLL), Systemon-Chip (SoC), Phase Locked Loop (PLL), Very High speedIntegrated Circuit (VHSIC) Hardware Description Language(VHDL), Digitally Controlled Oscillator (DCO), Phase frequencydetector (PFD) and Voltage Controlled Oscillator (VCO).

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489 MPC of Single Phase Inverter for PV System

Authors: Irtaza M. Syed, Kaamran Raahemifar

Abstract:

This paper presents a model predictive control (MPC) of a utility interactive (UI) single phase inverter (SPI) for a photovoltaic (PV) system at residential/distribution level. The proposed model uses single-phase phase locked loop (PLL) to synchronize SPI with the grid and performs MPC control in a dq reference frame. SPI model consists of boost converter (BC), maximum power point tracking (MPPT) control, and a full bridge (FB) voltage source inverter (VSI). No PI regulators to tune and carrier and modulating waves are required to produce switching sequence. Instead, the operational model of VSI is used to synthesize sinusoidal current and track the reference. Model is validated using a three kW PV system at the input of UI-SPI in Matlab/Simulink. Implementation and results demonstrate simplicity and accuracy, as well as reliability of the model.

Keywords: Matlab/Simulink, Model Predictive Control, Phase Locked Loop, Single Phase Inverter, Voltage Source Inverter.

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488 Design of High Gain, High Bandwidth Op-Amp for Reduction of Mismatch Currents in Charge Pump PLL in 180 nm CMOS Technology

Authors: R .H. Talwekar, S. S Limaye

Abstract:

The designing of charge pump with high gain Op- Amp is a challenging task for getting faithful response .Design of high performance phase locked loop require ,a design of high performance charge pump .We have designed a operational amplifier for reducing the error caused by high speed glitch in a transistor and mismatch currents . A separate Op-Amp has designed in 180 nm CMOS technology by CADENCE VIRTUOSO tool. This paper describes the design of high performance charge pump for GHz CMOS PLL targeting orthogonal frequency division multiplexing (OFDM) application. A high speed low power consumption Op-Amp with more than 500 MHz bandwidth has designed for increasing the speed of charge pump in Phase locked loop.

Keywords: Charge pump (CP) Orthogonal frequency divisionmultiplexing (OFDM), Phase locked loop (PLL), Phase frequencydetector (PFD), Voltage controlled oscillator (VCO),

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487 Charge-Pump with a Regulated Cascode Circuit for Reducing Current Mismatch in PLLs

Authors: Jae Hyung Noh, Hang Geun Jeong

Abstract:

The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discharging current causes phase offset and reference spurs in a PLL. We propose a new charge-pump circuit to reduce the current mismatch by using a regulated cascode circuit. The proposed charge-pump circuit is designed and simulated by spectre with TSMC 0.18-μm 1.8-V CMOS technology.

Keywords: Phase-locked loop (PLL), charge-pump, phase/frequency detector (PFD), regulated cascode.

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486 Bipolar PWM and LCL Filter Configuration to Reduce Leakage Currents in Transformerless PV System Connected to Utility Grid

Authors: Shanmuka Naga Raju

Abstract:

This paper  presents PV system without considering transformer connected to electric grid. This is considered more economic compared to present PV system. The problem that occurs when transformer is not considered appears with a leakage current near capacitor connected to ground. Bipolar Pulse Width Modulation (BPWM) technique along with filter L-C-L configuration in the circuit is modeled to shrink the leakage current in the circuit. The DC/AC inverter is modeled using H-bridge Insulated Gate Bipolar Transistor (IGBT) module which is controlled using proposed Bipolar PWM control technique. To extract maximum power, Maximum Power Point Technique (MPPT) controller is used in this model. Voltage and current regulators are used to determine the reference voltage for the inverter from active and reactive current where reactive current is set to zero. The PLL is modeled to synchronize the measurements. The model is designed with MATLAB Simulation blocks and compared with the methods available in literature survey to show its effectiveness.

Keywords: Photovoltaic, PV, pulse width modulation, PWM, perturb and observe, phase locked loop.

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485 On-Chip Aging Sensor Circuit Based on Phase Locked Loop Circuit

Authors: Ararat Khachatryan, Davit Mirzoyan

Abstract:

In sub micrometer technology, the aging phenomenon starts to have a significant impact on the reliability of integrated circuits by bringing performance degradation. For that reason, it is important to have a capability to evaluate the aging effects accurately. This paper presents an accurate aging measurement approach based on phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuit. The architecture is rejecting the circuit self-aging effect from the characteristics of PLL, which is generating the frequency without any aging phenomena affects. The aging monitor is implemented in low power 32 nm CMOS technology, and occupies a pretty small area. Aging simulation results show that the proposed aging measurement circuit improves accuracy by about 2.8% at high temperature and 19.6% at high voltage.

Keywords: Nanoscale, aging, effect, NBTI, HCI.

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484 A Programmable FSK-Modulator in 350nm CMOS Technology

Authors: Nasir Mehmood, Saad Rahman, Vinodh Ravinath, Mahesh Balaji

Abstract:

This paper describes the design of a programmable FSK-modulator based on VCO and its implementation in 0.35m CMOS process. The circuit is used to transmit digital data at 100Kbps rate in the frequency range of 400-600MHz. The design and operation of the modulator is discussed briefly. Further the characteristics of PLL, frequency synthesizer, VCO and the whole design are elaborated. The variation among the proposed and tested specifications is presented. Finally, the layout of sub-modules, pin configurations, final chip and test results are presented.

Keywords: FSK Modulator, CMOS, VCO, Phase Locked Loop, Frequency Synthesizer.

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483 Software Digital Phase-locked Loop for Induction Motor Speed Control

Authors: Benmabrouk. Zaineb, Ben Hamed. Mouna, Lassad. Sbita

Abstract:

This article deals to describe the simulation investigation of the digital phase locked loop implemented in software (SDPLL). SDPLL has been developed for speed drives of an induction motor in scalar strategy. A drive was implemented and simulation results are presented to verify the robustness against motor parameter variation and regulation speed.

Keywords: Induction motor, Software Digital Phase LockedLoop, Speed control, Simulation.

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482 A High Time Resolution Digital Pulse Width Modulator Based on Field Programmable Gate Array’s Phase Locked Loop Megafunction

Authors: Jun Wang, Tingcun Wei

Abstract:

The digital pulse width modulator (DPWM) is the crucial building block for digitally-controlled DC-DC switching converter, which converts the digital duty ratio signal into its analog counterpart to control the power MOSFET transistors on or off. With the increase of switching frequency of digitally-controlled DC-DC converter, the DPWM with higher time resolution is required. In this paper, a 15-bits DPWM with three-level hybrid structure is presented; the first level is composed of a7-bits counter and a comparator, the second one is a 5-bits delay line, and the third one is a 3-bits digital dither. The presented DPWM is designed and implemented using the PLL megafunction of FPGA (Field Programmable Gate Arrays), and the required frequency of clock signal is 128 times of switching frequency. The simulation results show that, for the switching frequency of 2 MHz, a DPWM which has the time resolution of 15 ps is achieved using a maximum clock frequency of 256MHz. The designed DPWM in this paper is especially useful for high-frequency digitally-controlled DC-DC switching converters.

Keywords: DPWM, PLL megafunction, FPGA, time resolution, digitally-controlled DC-DC switching converter.

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481 Digital Encoder Based Power Frequency Deviation Measurement

Authors: Syed Javed Arif, Mohd Ayyub Khan, Saleem Anwar Khan

Abstract:

In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.

Keywords: Frequency measurement, digital control, phase locked loop, encoding, Verilog HDL.

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480 An Optimization Tool-Based Design Strategy Applied to Divide-by-2 Circuits with Unbalanced Loads

Authors: Agord M. Pinto Jr., Yuzo Iano, Leandro T. Manera, Raphael R. N. Souza

Abstract:

This paper describes an optimization tool-based design strategy for a Current Mode Logic CML divide-by-2 circuit. Representing a building block for output frequency generation in a RFID protocol based-frequency synthesizer, the circuit was designed to minimize the power consumption for driving of multiple loads with unbalancing (at transceiver level). Implemented with XFAB XC08 180 nm technology, the circuit was optimized through MunEDA WiCkeD tool at Cadence Virtuoso Analog Design Environment ADE.

Keywords: Divide-by-2 circuit, CMOS technology, PLL phase locked-loop, optimization tool, CML current mode logic, RF transceiver.

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479 Control Algorithm for Shunt Active Power Filter using Synchronous Reference Frame Theory

Authors: Consalva J. Msigwa, Beda J. Kundy, Bakari M. M. Mwinyiwiwa,

Abstract:

This paper presents a method for obtaining the desired reference current for Voltage Source Converter (VSC) of the Shunt Active Power Filter (SAPF) using Synchronous Reference Frame Theory. The method relies on the performance of the Proportional-Integral (PI) controller for obtaining the best control performance of the SAPF. To improve the performance of the PI controller, the feedback path to the integral term is introduced to compensate the winding up phenomenon due to integrator. Using Reference Frame Transformation, reference signals are transformed from a - b - c stationery frame to 0 - d - q rotating frame. Using the PI controller, the reference signals in the 0 - d - q rotating frame are controlled to get the desired reference signals for the Pulse Width Modulation. The synchronizer, the Phase Locked Loop (PLL) with PI filter is used for synchronization, with much emphasis on minimizing delays. The system performance is examined with Shunt Active Power Filter simulation model.

Keywords: Phase Locked Loop (PLL), Voltage Source Converter (VSC), Shunt Active Power Filter (SAPF), PI, Pulse Width Modulation (PWM)

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478 Improving the Shunt Active Power Filter Performance Using Synchronous Reference Frame PI Based Controller with Anti-Windup Scheme

Authors: Consalva J. Msigwa, Beda J. Kundy, Bakari M. M. Mwinyiwiwa

Abstract:

In this paper the reference current for Voltage Source Converter (VSC) of the Shunt Active Power Filter (SAPF) is generated using Synchronous Reference Frame method, incorporating the PI controller with anti-windup scheme. The proposed method improves the harmonic filtering by compensating the winding up phenomenon caused by the integral term of the PI controller. Using Reference Frame Transformation, the current is transformed from om a - b - c stationery frame to rotating 0 - d - q frame. Using the PI controller, the current in the 0 - d - q frame is controlled to get the desired reference signal. A controller with integral action combined with an actuator that becomes saturated can give some undesirable effects. If the control error is so large that the integrator saturates the actuator, the feedback path becomes ineffective because the actuator will remain saturated even if the process output changes. The integrator being an unstable system may then integrate to a very large value, the phenomenon known as integrator windup. Implementing the integrator anti-windup circuit turns off the integrator action when the actuator saturates, hence improving the performance of the SAPF and dynamically compensating harmonics in the power network. In this paper the system performance is examined with Shunt Active Power Filter simulation model.

Keywords: Phase Locked Loop (PLL), Voltage SourceConverter (VSC), Shunt Active Power Filter (SAPF), PI, Pulse WidthModulation (PWM).

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477 20 GHz Fractional Phased Locked Loop Circuit for the Gbps Wireless Communication

Authors: Ki-Jin Kim, Sanghoon Park, K. H. Ahn

Abstract:

This paper presents the 20-GHz fractional PLL (Phase Locked Loop) circuit for the next generation Wi-Fi by using 90 nm TSMC process. The newly suggested millimeter wave 16/17 pre-scalar is designed and verified by measurement to make the fractional PLL having a low quantization noise. The operational bandwidth of the 60 GHz system is 15 % of the carrier frequency which requires large value of Kv (VCO control gain) resulting in degradation of phase noise. To solve this problem, this paper adopts AFC (Automatic Frequency Controller) controlled 4-bit millimeter wave VCO with small value of Kv. Also constant Kv is implemented using 4-bit varactor bank. The measured operational bandwidth is 18.2 ~ 23.2 GHz which is 25 % of the carrier frequency. The phase noise of -58 and -96.2 dBc/Hz at 100 KHz and 1 MHz offset is measured respectively. The total power consumption of the PLL is only 30 mW.

Keywords: Millimeter Wave Fractional PLL, Wide band VCO, WPAN Transceiver.

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476 Verification of a Locked CFD Approach to Cool Down Modeling

Authors: P. Bárta

Abstract:

Increasing demand on the performance of Subsea Production Systems (SPS) suggests a need for more detailed investigation of fluid behavior taking place in subsea equipment. Complete CFD cool down analyses of subsea equipment are very time demanding. The objective of this paper is to investigate a Locked CFD approach, which enables significant reduction of the computational time and at the same time maintains sufficient accuracy during thermal cool down simulations. The result comparison of a dead leg simulation using the Full CFD and the three LCFD-methods confirms the validity of the locked flow field assumption for the selected case. For the tested case the LCFD simulation speed up by factor of 200 results in the absolute thermal error of 0.5 °C (3% relative error), speed up by factor of 10 keeps the LCFD results within 0.1 °C (0.5 % relative error) comparing to the Full CFD.

Keywords: CFD, Locked Flow Field, Speed up of CFD simulation time, Subsea

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475 Study on Liquid Nitrogen Gravity Circulation Loop for Cryopumps in Large Space Simulator

Authors: Weiwei Shan, Wenjing Ding, Juan Ning, Chao He, Zijuan Wang

Abstract:

Gravity circulation loop for the cryopumps of the space simulator is introduced, and two phase mathematic model of flow heat transfer is analyzed as well. Based on this model, the liquid nitrogen (LN2) gravity circulation loop including its equipment and layout is designed and has served as LN2 feeding system for cryopumps in one large space simulator. With the help of control software and human machine interface, this system can be operated flexibly, simply, and automatically under four conditions. When running this system, the results show that the cryopumps can be cooled down and maintained under the required temperature, 120 K.

Keywords: Cryopumps, gravity circulation loop, liquid nitrogen, two-phase.

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474 Discrete-time Phase and Delay Locked Loops Analyses in Tracking Mode

Authors: Jiri Sebesta

Abstract:

Phase locked loops (PLL) and delay locked loops (DLL) play an important role in establishing coherent references (phase of carrier and symbol timing) in digital communication systems. Fully digital receiver including digital carrier synchronizer and symbol timing synchronizer fulfils the conditions for universal multi-mode communication receiver with option of symbol rate setting over several digit places and long-term stability of requirement parameters. Afterwards it is necessary to realize PLL and DLL in synchronizer in digital form and to approach to these subsystems as a discrete representation of analog template. Analysis of discrete phase locked loop (DPLL) or discrete delay locked loop (DDLL) and technique to determine their characteristics based on analog (continuous-time) template is performed in this posed paper. There are derived transmission response and error function for 1st order discrete locked loop and resulting equations and graphical representations for 2nd order one. It is shown that the spectrum translation due to sampling takes effect at frequency characteristics computing for specific values of loop parameters.

Keywords: Carrier synchronization, coherent demodulation, software defined receiver, symbol timing.

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473 Independent Design of Multi-loop PI/PID Controllers for Multi-delay Processes

Authors: Truong Nguyen Luan Vu, Moonyong Lee

Abstract:

The interactions between input/output variables are a very common phenomenon encountered in the design of multi-loop controllers for interacting multivariable processes, which can be a serious obstacle for achieving a good overall performance of multiloop control system. To overcome this impediment, the decomposed dynamic interaction analysis is proposed by decomposing the multiloop control system into a set of n independent SISO systems with the corresponding effective open-loop transfer function (EOTF) within the dynamic interactions embedded explicitly. For each EOTF, the reduced model is independently formulated by using the proposed reduction design strategy, and then the paired multi-loop proportional-integral-derivative (PID) controller is derived quite simply and straightforwardly by using internal model control (IMC) theory. This design method can easily be implemented for various industrial processes because of its effectiveness. Several case studies are considered to demonstrate the superior of the proposed method.

Keywords: Multi-loop PID controller, internal model control(IMC), effective open-loop transfer function (EOTF)

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472 Effect of Loop Diameter, Height and Insulation on a High Temperature CO2 Based Natural Circulation Loop

Authors: S. Sadhu, M. Ramgopal, S. Bhattacharyya

Abstract:

Natural circulation loops (NCLs) are buoyancy driven flow systems without any moving components. NCLs have vast applications in geothermal, solar and nuclear power industry where reliability and safety are of foremost concern. Due to certain favorable thermophysical properties, especially near supercritical regions, carbon dioxide can be considered as an ideal loop fluid in many applications. In the present work, a high temperature NCL that uses supercritical carbon dioxide as loop fluid is analysed. The effects of relevant design and operating variables on loop performance are studied. The system operating under steady state is modelled taking into account the axial conduction through loop fluid and loop wall, and heat transfer with surroundings. The heat source is considered to be a heater with controlled heat flux and heat sink is modelled as an end heat exchanger with water as the external cold fluid. The governing equations for mass, momentum and energy conservation are normalized and are solved numerically using finite volume method. Results are obtained for a loop pressure of 90 bar with the power input varying from 0.5 kW to 6.0 kW. The numerical results are validated against the experimental results reported in the literature in terms of the modified Grashof number (Grm) and Reynolds number (Re). Based on the results, buoyancy and friction dominated regions are identified for a given loop. Parametric analysis has been done to show the effect of loop diameter, loop height, ambient temperature and insulation. The results show that for the high temperature loop, heat loss to surroundings affects the loop performance significantly. Hence this conjugate heat transfer between the loop and surroundings has to be considered in the analysis of high temperature NCLs.

Keywords: Conjugate heat transfer, heat loss, natural circulation loop, supercritical carbon dioxide.

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471 Satellite Thermal Control: Cooling by a Diphasic Loop

Authors: L. Boukhris, A. Boudjemai, A. Bellar, R. Roubache, M. Bensaada

Abstract:

In space during functioning, a satellite will be heated up due to the behavior of its components such as power electronics. In order to prevent problems in the satellite, this heat has to be released in space thanks to the cooling system. This system consists of a loop heat pipe (LHP), in which a fluid streams through an evaporator and a condenser. In the evaporator, the fluid captures the heat from the satellite and evaporates. Then it flows to the condenser where it releases the heat and it condenses. In this project, the two mains parts of a cooling system are studied: the evaporator and the condenser. The study of the diphasic loop was done starting from digital simulations carried out under Matlab and Femlab.

Keywords: capillarity, condenser, evaporator, phase change, transfer of heat.

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470 Phase Equilibrium in Aqueous Two-phase Systems Containing Poly (propylene glycol) and Sodium Citrate at Different pH

Authors: Farshad Rahimpour, Ali Reza Baharvand

Abstract:

The phase diagrams and compositions of coexisting phases have been determined for aqueous two-phase systems containing poly(propylene glycol) with average molecular weight of 425 and sodium citrate at various pH of 3.93, 4.44, 4.6, 4.97, 5.1, 8.22. The effect of pH on the salting-out effect of poly (propylene glycol) by sodium citrate has been studied. It was found that, an increasing in pH caused the expansion of two-phase region. Increasing pH also increases the concentration of PPG in the PPGrich phase, while the salt-rich phase will be somewhat mole diluted.

Keywords: Aqueous two-phase system, Phase equilibrium, Biomolecules purification

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469 A Closed-Loop Design Model for Sustainable Manufacturing by Integrating Forward Design and Reverse Design

Authors: Yuan-Jye Tseng, Yi-Shiuan Chen

Abstract:

In this paper, a new concept of closed-loop design for a product is presented. The closed-loop design model is developed by integrating forward design and reverse design. Based on this new concept, a closed-loop design model for sustainable manufacturing by integrated evaluation of forward design, reverse design, and green manufacturing using a fuzzy analytic network process is developed. In the design stage of a product, with a given product requirement and objective, there can be different ways to design the detailed components and specifications. Therefore, there can be different design cases to achieve the same product requirement and objective. Subsequently, in the design evaluation stage, it is required to analyze and evaluate the different design cases. The purpose of this research is to develop a model for evaluating the design cases by integrated evaluating the criteria in forward design, reverse design, and green manufacturing. A fuzzy analytic network process method is presented for integrated evaluation of the criteria in the three models. The comparison matrices for evaluating the criteria in the three groups are established. The total relational values among the three groups represent the total relational effects. In applications, a super matrix model is created and the total relational values can be used to evaluate the design cases for decision-making to select the final design case. An example product is demonstrated in this presentation. It shows that the model is useful for integrated evaluation of forward design, reverse design, and green manufacturing to achieve a closed-loop design for sustainable manufacturing objective.

Keywords: Design evaluation, forward design, reverse design, closed-loop design, supply chain management, closed-loop supply chain, fuzzy analytic network process.

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468 Loop Heat Pipe: Simple Thermodynamic

Authors: Mohammad Hamdan, Emad Elnajjar

Abstract:

The LHP is a two-phase device with extremely high effective thermal conductivity that utilizes the thermodynamic pressure difference to circulate a cooling fluid. A thermodynamics analytical model is developed to explore different parameters effects on a Loop Heat Pipe (LHP).. The effects of pipe length, pipe diameter, condenser temperature, and heat load are reported. As pipe length increases and/or pipe diameter decreases, a higher temperature is expected in the evaporator.

Keywords: Loop Heat Pipe, LHP, Passive Cooling, CapillaryForce.

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467 Investigation of Cascade Loop Heat Pipes

Authors: Nandy Putra, Atrialdipa Duanovsah, Kristofer Haliansyah

Abstract:

The aim of this research is to design a LHP with low thermal resistance and low condenser temperature. A Self-designed cascade LHP was tested by using biomaterial, sintered copper powder, and aluminum screen mesh as the wick. Using pure water as the working fluid for the first level of the LHP and 96% alcohol as the working fluid for the second level of LHP, the experiments were run with 10W, 20W, and 30W heat input. Experimental result shows that the usage of biomaterial as wick could reduce more temperature at evaporator than by using sintered copper powder and screen mesh up to 22.63% and 37.41% respectively. The lowest thermal resistance occurred during the usage of biomaterial as wick of heat pipe, which is 2.06 oC/W. The usage of cascade system could be applied to LHP to reduce the temperature at condenser and reduced thermal resistance up to 17.6%.

Keywords: Biomaterial, cascade loop heat pipe, screen mesh, sintered Cu.

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466 The Effect of Guanidine Hydrochloride on Phase Diagram of PEG- Phosphate Aqueous Two-Phase System

Authors: Farshad Rahimpour, Mohsen Pirdashti

Abstract:

This report focus on phase behavior of polyethylene glycol (PEG)4000/ phosphate/ guanidine hydrochloride/ water system at different guanidine hydrochloride concentrations and pH. The binodal of the systems was displaced toward higher concentrations of the components with increasing guanidine hydrochloride concentrations. The partition coefficient of guanidine hydrochloride was near unity and increased with decreasing pH and increasing PEG/salt (%w/w) ratio.

Keywords: Aqueous two-phase system, guanidinehydrochloride, partition coefficient, phase diagram.

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465 A Servo Control System Using the Loop Shaping Design Procedure

Authors: Naohiro Ban, Hiromitsu Ogawa, Manato Ono, Yoshihisa Ishida

Abstract:

This paper describes an expanded system for a servo system design by using the Loop Shaping Design Procedure (LSDP). LSDP is one of the H∞ design procedure. By conducting Loop Shaping with a compensator and robust stabilization to satisfy the index function, we get the feedback controller that makes the control system stable. In this paper, we propose an expanded system for a servo system design and apply to the DC motor. The proposed method performs well in the DC motor positioning control. It has no steady-state error in the disturbance response and it has robust stability.

Keywords: Loop Shaping Design Procedure (LSDP), servosystem, DC motor.

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464 Feasibility Study on Designing a Flat Loop Heat Pipe (LHP) to Recover the Heat from Exhaust of a Gas Turbine

Authors: M.H.Ghaffari

Abstract:

A theoretical study is conducted to design and explore the effect of different parameters such as heat loads, the tube size of piping system, wick thickness, porosity and hole size on the performance and capability of a Loop Heat Pipe(LHP). This paper presents a steady state model that describes the different phenomena inside a LHP. Loop Heat Pipes(LHPs) are two-phase heat transfer devices with capillary pumping of a working fluid. By their original design comparing with heat pipes and special properties of the capillary structure, they-re capable of transferring heat efficiency for distances up to several meters at any orientation in the gravity field, or to several meters in a horizontal position. This theoretical model is described by different relations to satisfy important limits such as capillary and nucleate boiling. An algorithm is developed to predict the size of the LHP satisfying the limitations mentioned above for a wide range of applied loads. Finally, to assess and evaluate the algorithm and all the relations considered, we have used to design a new kind of LHP to recover the heat from the exhaust of an actual Gas Turbine. By finding the results, it showed that we can use the LHP as a very high efficient device to recover the heat even in high amount of loads(exhaust of a gas turbine). The sizes of all parts of the LHP were obtained using the developed algorithm.

Keywords: Loop Heat Pipe, Head Load, Liquid-Vapor Interface, Heat Transfer, Design Algorithm

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463 Experimental Investigation and Optimization of Nanoparticle Mass Concentration and Heat Input of Loop Heat Pipe

Authors: P. Gunnasegaran, M. Z. Abdullah, M. Z. Yusoff, Nur Irmawati

Abstract:

This study presents experimental and optimization of nanoparticle mass concentration and heat input based on the total thermal resistance (Rth) of loop heat pipe (LHP), employed for PCCPU cooling. In this study, silica nanoparticles (SiO2) in water with particle mass concentration ranged from 0% (pure water) to 1% is considered as the working fluid within the LHP. The experimental design and optimization is accomplished by the design of experimental tool, Response Surface Methodology (RSM). The results show that the nanoparticle mass concentration and the heat input have significant effect on the Rth of LHP. For a given heat input, the Rth is found to decrease with the increase of the nanoparticle mass concentration up to 0.5% and increased thereafter. It is also found that the Rth is decreased when the heat input is increased from 20W to 60W. The results are optimized with the objective of minimizing the Rth, using Design-Expert software, and the optimized nanoparticle mass concentration and heat input are 0.48% and 59.97W, respectively, the minimum thermal resistance being 2.66 (ºC/W).

Keywords: Loop heat pipe, nanofluid, optimization, thermal resistance.

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462 The Framework of System Safety for Multi Human-in-The-Loop System

Authors: Hideyuki Shintani, Ichiro Koshijima

Abstract:

In Cyber Physical System (CPS), if there are a large number of persons in the process, a role of person in CPS might be different comparing with the one-man system. It is also necessary to consider how Human-in-The-Loop Cyber Physical Systems (HiTLCPS) ensure safety of each person in the loop process. In this paper, the authors discuss a system safety framework with an illustrative example with STAMP model to clarify what point for safety should be considered and what role of person in the should have.

Keywords: Cyber Physical System, Human-in-The-Loop, Safety, STAMP model.

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