Search results for: Very High Speed Integrated Circuits HardwareDescription Language (VHDL)

Authors: Manop Vorasri, Komson Jirapattarasilp, Sittichai Kaewkuekool

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The objective of this research was to study factors, which were affected on surface roughness in high speed milling of hardened tool steel. Material used in the experiment was tool steel JIS SKD 61 that hardened on 60 ±2 HRC. Full factorial experimental design was conducted on 3 factors and 3 levels (3 3 designs) with 2 replications. Factors were consisted of cutting speed, feed rate, and depth of cut. The results showed that influenced factor affected to surface roughness was cutting speed, feed rate and depth of cut which showed statistical significant. Higher cutting speed would cause on better surface quality. On the other hand, higher feed rate would cause on poorer surface quality. Interaction of factor was found that cutting speed and depth of cut were significantly to surface quality. The interaction of high cutting speed associated with low depth of cut affected to better surface quality than low cutting speed and high depth of cut.

Keywords: High-speed milling, Tool steel, SKD 61 Steel, Surface roughness, Cutting speed, Feed rate, Depth of cut

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Authors: G. Ait Abdelmalek, R. Ziani

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In this document, we have proposed a robust conceptual strategy, in order to improve the robustness against the manufacturing defects and thus the reliability of logic CMOS circuits. However, in order to enable the use of future CMOS technology nodes this strategy combines various types of design: DFR (Design for Reliability), techniques of tolerance: hardware redundancy TMR (Triple Modular Redundancy) for hard error tolerance, the DFT (Design for Testability. The Results on largest ISCAS and ITC benchmark circuits show that our approach improves considerably the reliability, by reducing the key factors, the area costs and fault tolerance probability.

Keywords: Design for reliability, design for testability, fault tolerance, manufacturing yield.

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Authors: Zdenek Bohuslavek

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Development of microprocessor controlled sensor for measurement of wind speed and direction is the aim of this study. Electrical circuits and software were developed to the existing electromechanical part of the sensor TM-W2 becoming the properties of so-called smart sensor. The measured data about wind speed (sensitivity 0.01 m/s) and direction (0-360° by step 10°) are transmitted as 16-bit information. The connection between sensor and control unit is realized by radio communication (FM 433 MHz). Transition range is 220 m if used Quad type antenna. This concept provides substitution of actual cable systems by wireless ones.

Keywords: smart wind sensor, anemometer, wind speed, wireless communication

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Authors: Chalermsak Leetrakool, Komson Jirapattarasilp

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This research was to study effect of rotational speed and eccentric factors, which were affected on looseness of bearing. The experiment was conducted on three rotational speeds and five eccentric distances with 5 replications. The results showed that influenced factor affected to looseness of bearing was rotational speed and eccentric distance which showed statistical significant. Higher rotational speed would cause on high looseness. Moreover, more eccentric distance, more looseness of bearing. Using bearing at high rotational with high eccentric of shaft would be affected bearing fault more than lower rotational speed. The prediction equation of looseness was generated by regression analysis. The prediction has an effected to the looseness of bearing at 91.5%.

Keywords: Bearing, Looseness, Rotational speed, Eccentric

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Authors: Shashank Gautam, Pramod Sharma

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In present era, development of digital circuits, signal processors and other integrated circuits, magnitude comparators are challenged by large area and more power consumption. Comparator is most basic circuit that performs comparison. This paper presents a technique to design a two bit comparator which consumes less area and power. DSCH and MICROWIND version 3 are used to design the schematic and design the layout of the schematic, observe the performance parameters at different nanometer technologies respectively.

Keywords: Chip design, consumed power, layout area, two bit comparator.

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Authors: Yukinari Minagi , Akinori Kanasugi

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This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operation. The proposed arithmetic circuit performs floating-point arithmetic which is frequently used in science and technology. The data format is floating-point based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

Keywords: dynamic reconfiguration, floating-point arithmetic, double precision, FPGA

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Authors: Shiyang Zhu, G. Q. Lo, D. L. Kwong

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Silicon photonics has generated an increasing interest in recent years mainly for optical communications optical interconnects in microelectronic circuits or bio-sensing applications. The development of elementary passive and active components (including detectors and modulators), which are mainly fabricated on the silicon on insulator platform for CMOS-compatible fabrication, has reached such a performance level that the integration challenge of silicon photonics with microelectronic circuits should be addressed. Since crystalline silicon can only be grown from another silicon crystal, making it impossible to deposit in this state, the optical devices are typically limited to a single layer. An alternative approach is to integrate a photonic layer above the CMOS chip using back-end CMOS fabrication process. In this paper, various materials, including silicon nitride, amorphous silicon, and polycrystalline silicon, for this purpose are addressed.

Keywords: Silicon photonics, CMOS, Integration.

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Authors: Jana Novakova, Lenka Petrkovska, Josef Brychta, Robert Cep, Lenka Ocenasova

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The contribution is dealing with the influence of high speed parameters on the quality of machined surface. In general the principle of high speed cutting lies in achieving faster machine times with concurrent increase in accuracy and quality of the machined areas in largely irregular, mathematically hard to define shapes. High speed machining is a highly effective method of machining with the following goals: increasing of machining productivity, increasing of quality of the machined surface, improving of machining economy, improving of ecological aspects of machining. This article is based on an experiment performed by the Department of Machining and Assembly of the Faculty of Mechanical Engineering of VŠBTechnical University of Ostrava.

Keywords: High speed cutting, measurement, surface integrity, surface roughness, residual stress/

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Authors: M. T. Anwar, P. K. Lala, P. Thenappan

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This paper presents the decoder design for the single error correcting and double error detecting code proposed by the authors in an earlier paper. The speed of error detection and correction of a code is largely dependent upon the associated encoder and decoder circuits. The complexity and the speed of such circuits are determined by the number of 1?s in the parity check matrix (PCM). The number of 1?s in the parity check matrix for the code proposed by the authors are fewer than in any currently known single error correcting/double error detecting code. This results in simplified encoding and decoding circuitry for error detection and correction.

Keywords: Decoder, Hsiao code, Parity Check Matrix, Syndrome Pattern.

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Authors: Abdulatif A. M. Shaban

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Transient simulation of power electronic circuits is of considerable interest to the designer. The switching nature of the devices used permits development of specialized algorithms which allow a considerable reduction in simulation time compared to general purpose simulation algorithms. This paper describes a method used to simulate a power electronic circuits using the SIMULINK toolbox within MATLAB software. Theoretical results are presented provides the basis of transient analysis of a power electronic circuits.

Keywords: Modelling, Simulation.

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Authors: Zhi Teng, Ye Liu, Fuji Ren

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The main aim of this research is to investigate a novel technique for implementing a more natural and intelligent conversation system. Conversation systems are designed to converse like a human as much as their intelligent allows. Sometimes, we can think that they are the embodiment of Turing-s vision. It usually to return a predetermined answer in a predetermined order, but conversations abound with uncertainties of various kinds. This research will focus on an integrated natural language processing approach. This approach includes an integrated knowledge-base construction module, a conversation understanding and generator module, and a state manager module. We discuss effectiveness of this approach based on an experiment.

Keywords: Conversation System, integrated knowledge-base construction, conversation understanding and generator, state manager

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Authors: S. Yordchim, G. Anugkakul, T. Gibbs

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The English competence of Thai people was examined in the context of knowledge of English in everyday life for Small and Medium Entrepreneurs (SMEs), and also integrated with Second language acquisition (SLA) students’ classroom. Second language acquisition was applied to the results of the questionnaires and interview forms. Levels of the need on English used for SME entrepreneurs in Thailand, satisfaction on joining the street classroom project were shown to be significantly high for some certain language functions and satisfaction. Finding suggests that the language functions on etiquette for professional use is essential and useful because lesson learned can be used in the real situation for their career. Implications for the climate of the street classroom are discussed.

Keywords: English classroom, second language acquisition, Small and Medium Entrepreneurs, Thai students.

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Authors: Mansi Jhamb, R. K. Sharma, A. K. Gupta

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The distribution of a single global clock across a chip has become the major design bottleneck for high performance VLSI systems owing to the power dissipation, process variability and multicycle cross-chip signaling. A Network-on-Chip (NoC) architecture partitioned into several synchronous blocks has become a promising approach for attaining fine-grain power management at the system level. In a NoC architecture the communication between the blocks is handled asynchronously. To interface these blocks on a chip operating at different frequencies, an asynchronous FIFO interface is inevitable. However, these asynchronous FIFOs are not required if adjacent blocks belong to the same clock domain. In this paper, we have designed and analyzed a 16-bit asynchronous micropipelined FIFO of depth four, with the awareness of place and route on an FPGA device. We have used a commercially available Spartan 3 device and designed a high speed implementation of the asynchronous 4-phase micropipeline. The asynchronous FIFO implemented on the FPGA device shows 76 Mb/s throughput and a handshake cycle of 109 ns for write and 101.3 ns for read at the simulation under the worst case operating conditions (voltage = 0.95V) on a working chip at the room temperature.

Keywords: Asynchronous, FIFO, FPGA, GALS, Network-on- Chip (NoC), VHDL.

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Authors: Jung-Ho Moon, Tae Kwon Ha

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In the present study, M2 high speed steels were fabricated by using electro-slag rapid remelting process. Carbide structure was analysed and the fracture toughness and hardness were also measured after austenitization treatment at 1190 and 1210oC followed by tempering treatment at 535oC for billets with various diameters from 16 to 60 mm. Electro-slag rapid remelting (ESRR) process is an advanced ESR process combined by continuous casting and successfully employed in this study to fabricate a sound M2 high speed ingot. Three other kinds of commercial M2 high speed steels, produced by traditional method, were also analysed for comparison. Distribution and structure of eutectic carbides of the ESRR billet were found to be comparable to those of commercial alloy and so was the fracture toughness.

Keywords: High speed tool steel, eutectic carbide, microstructure, hardness, fracture toughness.

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Authors: Jun-Hyuk Choi, Joon Sung Park, Jung-Moo Seo, In-Soung Jung

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A brushless DC motor with integrated drive circuit for air management system is presented. Using magnetic equivalent circuit model a basic design of the motor is determined, and specific configurations are inspected thanks to finite element analysis. In order to reduce an unbalanced magnetic force in an axial direction, induced forces between a stator core and a permanent magnet are calculated with respect to the relative positions of them. For the high efficiency, and high power density, BLDC motor and drive are developed. Also vibration mode and eccentricity of a rotor are considered at the rated and maximum rotational speed Through the experimental results, a validity of the simulated one is confirmed.

Keywords: blower, BLDC, inverter

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Authors: Nasir Mehmood, Jens Ogniewski, Vinodh Ravinath

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This paper describes the design of a real-time audiorange digital oscilloscope and its implementation in 90nm CMOS FPGA platform. The design consists of sample and hold circuits, A/D conversion, audio and video processing, on-chip RAM, clock generation and control logic. The design of internal blocks and modules in 90nm devices in an FPGA is elaborated. Also the key features and their implementation algorithms are presented. Finally, the timing waveforms and simulation results are put forward.

Keywords: CMOS, VLSI, Oscilloscope, Field Programmable Gate Array (FPGA), VHDL, Video Graphics Array (VGA)

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Authors: Ali A. Mehna, Mohmed A. Ali, Ali S. Zayed

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A numbers of important developments have led to an increasing attractiveness for very high speed electrical machines (either motor or generator). Specifically the increasing switching speed of power electronics, high energy magnets, high strength retaining materials, better high speed bearings and improvements in design analysis are the primary drivers in a move to higher speed. The design challenges come in the mechanical design both in terms of strength and resonant modes and in the electromagnetic design particularly in respect of iron losses and ac losses in the various conducting parts including the rotor. This paper describes detailed design work which has been done on a 50,000 rpm, 50kW permanent magnet( PM) synchronous machine. It describes work on electromagnetic and rotor eddy current losses using a variety of methods including both 2D finite element analysis

Keywords: High speed, PM motor, rotor and stator losses, finiteelement analysis

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Authors: Yngvar Berg, Omid Mirmotahari

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In this paper we ultra low-voltage and high speed CMOS domino logic. For supply voltages below 500mV the delay for a ultra low-voltage NAND2 gate is aproximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch is much less than for conventional CMOS. Differential domino gates for AND/NAND and OR/NOR operation are presented.

Keywords: Low-voltage, high-speed, NAND, NOR, CMOS.

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Authors: Neeraj K. Chasta

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This paper presents an idea for analog current comparison which compares input signal and reference currents with high speed and accuracy. Proposed circuit utilizes amplification properties of common gate configuration, where voltage variations of input current are amplified and a compared output voltage is developed. Cascaded inverter stages are used to generate final CMOS compatible output voltage. Power consumption of circuit can be controlled by the applied gate bias voltage. The comparator is designed and studied at 180nm CMOS process technology for a supply voltage of 3V.

Keywords: Current Mode, Comparator, High Resolution, High Speed.

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Authors: K. Sivasubramanian, K. B. Jayanthi

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Floorplanning plays a vital role in the physical design process of Very Large Scale Integrated (VLSI) chips. It is an essential design step to estimate the chip area prior to the optimized placement of digital blocks and their interconnections. Since VLSI floorplanning is an NP-hard problem, many optimization techniques were adopted in the literature. In this work, a music-inspired Harmony Search (HS) algorithm is used for the fixed die outline constrained floorplanning, with the aim of reducing the total chip area. HS draws inspiration from the musical improvisation process of searching for a perfect state of harmony. Initially, B*-tree is used to generate the primary floorplan for the given rectangular hard modules and then HS algorithm is applied to obtain an optimal solution for the efficient floorplan. The experimental results of the HS algorithm are obtained for the MCNC benchmark circuits.

Keywords: Floor planning, harmony search, non-slicing floorplan, very large scale integrated circuits.

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Authors: M. Jalali Azizpour, H. Mohammadi majd

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In this paper, the wear of high speed steel hobs during hobbing has been studied. The wear mechanisms are strongly influenced by the choice of cutting speed. At moderate and high cutting speeds three major wear mechanisms were identified: abrasion, mild adhesive and severe adhesive. The microstructure and wear behavior of two high speed steel grades (M2 and ASP30) has been compared. In contrast, a variation in chemical composition or microstructure of HSS tool material generally did not change the dominant wear mechanism. However, the tool material properties determine the resistance against the operating wear mechanism and consequently the tool life. The metallographic analysis and wear measurement at the tip of hob teeth included scanning electron microscopy and stereoscope microscopy. Roughness profilometery is used for measuring the gear surface roughness.

Keywords: abrasion, adhesion, cutting speed, hobbing, wear mechanism

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Authors: Jayanthi Rajendran

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Experience is what makes a man perfect. Though we tend to learn many a different things in life through practice still we need to go an extra mile to gain experience which would be profitable only when it is integrated with regular practice. A clear phenomenal idea is that every teacher is a learner. The centralized idea of this paper would focus on the integrated practices carried out among the students of Jizan University which enhances learning through experiences. Integrated practices like student-directed activities, balanced curriculum, phonological based activities and use of consistent language would enlarge the vision and mission of students to earn experience through learning. Students who receive explicit instruction and guidance could practice the skills and strategies through student-directed activities such as peer tutoring and cooperative learning. The second effective practice is to use consistent language. Consistent language provides students a model for talking about the new concepts which also enables them to communicate without hindrances. Phonological awareness is an important early reading skill for all students. Students generally have phonemic awareness in their home language can often transfer that knowledge to a second language. And also a balanced curriculum requires instruction in all the elements of reading. Reading is the most effective skill when both basic and higher-order skills are included on a daily basis. Computer based reading and listening skills will empower students to understand language in a better way. English language learners can benefit from sound reading instruction even before they are fully proficient in English as long as the instruction is comprehensible. Thus, if students have to be well equipped in learning they should foreground themselves in various integrated practices through multifarious experience for which teachers are moderators and trainers. This type of learning prepares the students for a constantly changing society which helps them to meet the competitive world around them for better employability fulfilling the vision and mission of the institution.

Keywords: Consistent language, employability, phonological awareness, balanced curriculum.

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Authors: Kyria Rebeca Finardi

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The study discusses the role of foreign languages in general and of English in particular in the process of internationalization of higher education (IHE), defined as the intentional integration of an international, intercultural or global dimension in the purpose, function or offer of higher education. The study is bibliographical and offers a brief outline of the current political, economic and educational scenarios in Brazil, before discussing some possibilities and challenges for the development of multilingualism and IHE there. The theoretical background includes a review of Brazilian language and internationalization policies. The review and discussion concludes that the use of the Content and Language Integrated Learning (CLIL) approach and the Intercomprehension approach to foreign language teaching/learning are relevant alternatives to foster multilingualism in that context.

Keywords: Brazil, higher education, internationalization, multilingualism.

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Authors: Yong-Seo Koo, Jin-Woo Jung, Byung-Seok Lee, Dong-Su Kim, Yil-Suk Yang

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In this paper, a novel LVTSCR-based device for electrostatic discharge (ESD) protection of integrated circuits (ICs) is designed, fabricated and characterized. The proposed device is similar to the conventional LVTSCR but it has an embedded PMOSFET in the anode n-well to enhance the turn on speed, the clamping capability and the robustness. This is possible because the embedded PMOSFET provides the sub-path of ESD discharge current. The TLP, HBM and MM testing are carried out to verify the ESD performance of the proposed devices, which are fabricated in 0.35um (Bipolar-CMOS-DMOS) BCDMOS process. The device has the robustness of 70mA/um that is higher about 60mA/um than the LVTSCR, approximately.

Keywords: ESD Protection, grounded gate NMOS (GGNMOS), low trigger voltage SCR (LVTSCR)

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Authors: M. Zezou

Abstract:

This paper focuses on the design of a Massive Open Online Course (MOOC) about Content Language Integrated Learning (CLIL) and more specifically about how teachers can use CLIL as an educational approach incorporating technology in their teaching as well. All the four weeks of the MOOC will be presented and a step-by-step analysis of each lesson will be offered. Additionally, the paper includes detailed lesson plans about CLIL lessons with proposed CLIL activities and games in which technology plays a central part. The MOOC is structured based on certain criteria, in order to ensure success, as well as a positive experience that the learners need to have after completing this MOOC. It addresses to all language teachers who would like to implement CLIL into their teaching. In other words, it presents the methodology that needs to be followed so as to successfully carry out a CLIL lesson and achieve the learning objectives set at the beginning of the course. Firstly, in this paper, it is very important to give the definitions of MOOCs and LMOOCs, as well as to explore the difference between a structure-based MOOC (xMOOC) and a connectivist MOOC (cMOOC) and present the criteria of a successful MOOC. Moreover, the notion of CLIL will be explored, as it is necessary to fully understand this concept before moving on to the design of the MOOC. Onwards, the four weeks of the MOOC will be introduced as well as lesson plans will be presented: The type of the activities, the aims of each activity and the methodology that teachers have to follow. Emphasis will be placed on the role of technology in foreign language learning and on the ways in which we can involve technology in teaching a foreign language. Final remarks will be made and a summary of the main points will be offered at the end.

Keywords: Content language integrated learning, connectivist massive open online course, lesson plan, language MOOC, massive open online course criteria, massive open online course, technology, structure-based massive open online course.

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Authors: Fatma Belghith, Hassen Loukil, Nouri Masmoudi

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This paper presents the hardware design of a unified architecture to compute the 4x4, 8x8 and 16x16 efficient twodimensional (2-D) transform for the HEVC standard. This architecture is based on fast integer transform algorithms. It is designed only with adders and shifts in order to reduce the hardware cost significantly. The goal is to ensure the maximum circuit reuse during the computing while saving 40% for the number of operations. The architecture is developed using FIFOs to compute the second dimension. The proposed hardware was implemented in VHDL. The VHDL RTL code works at 240 MHZ in an Altera Stratix III FPGA. The number of cycles in this architecture varies from 33 in 4-point- 2D-DCT to 172 when the 16-point-2D-DCT is computed. Results show frequency improvements reaching 96% when compared to an architecture described as the direct transcription of the algorithm.

Keywords: HEVC, Modified Integer Transform, FPGA.

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Authors: A.R. Aswatha, T. Basavaraju, S. Sandeep Kumar

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Timing driven physical design, synthesis, and optimization tools need efficient closed-form delay models for estimating the delay associated with each net in an integrated circuit (IC) design. The total number of nets in a modern IC design has increased dramatically and exceeded millions. Therefore efficient modeling of interconnection is needed for high speed IC-s. This paper presents closed–form expressions for RC and RLC interconnection trees in current mode signaling, which can be implemented in VLSI design tool. These analytical model expressions can be used for accurate calculation of delay after the design clock tree has been laid out and the design is fully routed. Evaluation of these analytical models is several orders of magnitude faster than simulation using SPICE.

Keywords: IC design, RC/RLC Interconnection, VLSI Systems.

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Authors: A. Muthuramalingam, S. Himavathi, E. Srinivasan

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.Hardware realization of a Neural Network (NN), to a large extent depends on the efficient implementation of a single neuron. FPGA-based reconfigurable computing architectures are suitable for hardware implementation of neural networks. FPGA realization of ANNs with a large number of neurons is still a challenging task. This paper discusses the issues involved in implementation of a multi-input neuron with linear/nonlinear excitation functions using FPGA. Implementation method with resource/speed tradeoff is proposed to handle signed decimal numbers. The VHDL coding developed is tested using Xilinx XC V50hq240 Chip. To improve the speed of operation a lookup table method is used. The problems involved in using a lookup table (LUT) for a nonlinear function is discussed. The percentage saving in resource and the improvement in speed with an LUT for a neuron is reported. An attempt is also made to derive a generalized formula for a multi-input neuron that facilitates to estimate approximately the total resource requirement and speed achievable for a given multilayer neural network. This facilitates the designer to choose the FPGA capacity for a given application. Using the proposed method of implementation a neural network based application, namely, a Space vector modulator for a vector-controlled drive is presented

Keywords: FPGA implementation, multi-input neuron, neural network, nn based space vector modulator.

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Authors: A. Aravind, M. Vetrivel, P. Abhimanyu, C. A. Akaash Emmanuel Raj, K. Sundararaj, V. R. S. Kumar

Abstract:

The choice of high-speed, low budget hatchback car with diversified options is increasing for meeting the new generation buyers trend. This paper is aimed to augment the current speed of the hatchback cars through the aerodynamic drag reduction technique. The inverted airfoils are facilitated at the bottom of the car for generating the downward force for negating the lift while increasing the current speed range for achieving a better road performance. The numerical simulations have been carried out using a 2D steady pressure-based    k-ɛ realizable model with enhanced wall treatment. In our numerical studies, Reynolds-averaged Navier-Stokes model and its code of solution are used. The code is calibrated and validated using the exact solution of the 2D boundary layer displacement thickness at the Sanal flow choking condition for adiabatic flows. We observed through the parametric analytical studies that the inverted airfoil integrated with the bottom surface at various predesigned locations of Hatchback cars can improve its overall aerodynamic efficiency through drag reduction, which obviously decreases the fuel consumption significantly and ensure an optimum road performance lucratively with maximum permissible speed within the framework of the manufactures constraints.

Keywords: Aerodynamics of commercial cars, downward force, hatchback car, inverted airfoil.

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Authors: Sara Sharifi Rad, Hassan Haghighi

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Due to important issues, such as deadlock, starvation, communication, non-deterministic behavior and synchronization, concurrent systems are very complex, sensitive, and error-prone. Thus ensuring reliability and accuracy of these systems is very essential. Therefore, there has been a big interest in the formal specification of concurrent programs in recent years. Nevertheless, some features of concurrent systems, such as dynamic process creation, scheduling and starvation have not been specified formally yet. Also, some other features have been specified partially and/or have been described using a combination of several different formalisms and methods whose integration needs too much effort. In other words, a comprehensive and integrated specification that could cover all aspects of concurrent systems has not been provided yet. Thus, this paper makes two major contributions: firstly, it provides a comprehensive formal framework to specify all well-known features of concurrent systems. Secondly, it provides an integrated specification of these features by using just a single formal notation, i.e., the Z language.

Keywords: Concurrent systems, Formal methods, Formal specification, Z language

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