Commenced in January 2007
Paper Count: 31107
Fast and Efficient On-Chip Interconnection Modeling for High Speed VLSI Systems
Abstract:Timing driven physical design, synthesis, and optimization tools need efficient closed-form delay models for estimating the delay associated with each net in an integrated circuit (IC) design. The total number of nets in a modern IC design has increased dramatically and exceeded millions. Therefore efficient modeling of interconnection is needed for high speed IC-s. This paper presents closed–form expressions for RC and RLC interconnection trees in current mode signaling, which can be implemented in VLSI design tool. These analytical model expressions can be used for accurate calculation of delay after the design clock tree has been laid out and the design is fully routed. Evaluation of these analytical models is several orders of magnitude faster than simulation using SPICE.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1330961Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1184
 R. Bashirullah, W. Liu, and R. Cavin, "Delay and power model for current-mode signaling in deep submicron global interconnects" Proceedings of IEEE Custom Integrated Circuits Conference, May 2002, pp. 513 -516.
 L.T. Pillage, R.A. Rohrer, "Asymptotic Waveform Evaluation for Timing Analysis,-- IEEE Trans. on CAD, Vol. 9, No. 4, April 1990, pp. 352-366.
 R. Achar, M.S. Nakhla, "Simulation of High-speed Interconnects," Proceedings of the IEEE, Vol. 89, No. 5, May 2001.
 C.W. Ho, A.E. Ruehli, P.A. Brennan, "The modified nodal approach to network analysis," IEEE Trans. Circuits and Systems, Vol. CAS-22, pp. 504- 509, June 1975.
 A Closed-form Delay Formula for On-Chip RLC Interconnects in Current-Mode Signaling Mingcui Zhou, Wentai Liu, Mohanasankar Sivaprakasam Department of Electrical Engineering, University of California at Santa Cruz, CA 95064, USA ┬®2005 IEEE.
 R. Venkatesan, J. Davis, and J. Meindl, "Compact distributed RLC interconnect models ---part IV: unified models for time delay, crosstalk, and repeater insertion," IEEE trans. Electron Devices, vol.50, no. 4, April, 2003, pp.1094-1102.
 H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
 Y. Ismail, E. Friedman, and J. Neves, "Figures of merit to characterize the importance of on-chip inductance," IEEE Trans. On VLSI System, vol. 7, no.4, December, 1999, pp. 442-449.
 A. Oppenheim, A.Willsky, and S. Nawab, Signal and System (1997), 2nd edition.