WASET
	%0 Journal Article
	%A A.R. Aswatha and  T. Basavaraju and  S. Sandeep Kumar
	%D 2008
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 14, 2008
	%T Fast and Efficient On-Chip Interconnection Modeling for High Speed VLSI Systems
	%U https://publications.waset.org/pdf/3788
	%V 14
	%X Timing driven physical design, synthesis, and
optimization tools need efficient closed-form delay models for
estimating the delay associated with each net in an integrated circuit
(IC) design. The total number of nets in a modern IC design has
increased dramatically and exceeded millions. Therefore efficient
modeling of interconnection is needed for high speed IC-s. This
paper presents closed–form expressions for RC and RLC
interconnection trees in current mode signaling, which can be
implemented in VLSI design tool. These analytical model
expressions can be used for accurate calculation of delay after the
design clock tree has been laid out and the design is fully routed.
Evaluation of these analytical models is several orders of magnitude
faster than simulation using SPICE.
	%P 243 - 246