An Improved Design of Area Efficient Two Bit Comparator

Authors: Shashank Gautam, Pramod Sharma

Abstract:

In present era, development of digital circuits, signal processors and other integrated circuits, magnitude comparators are challenged by large area and more power consumption. Comparator is most basic circuit that performs comparison. This paper presents a technique to design a two bit comparator which consumes less area and power. DSCH and MICROWIND version 3 are used to design the schematic and design the layout of the schematic, observe the performance parameters at different nanometer technologies respectively.

Keywords: Chip design, consumed power, layout area, two bit comparator.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1339600

References:

[1] Morgenshtein, A.; Fish, A.; Wagner, I.A., “Gate-diffusion input (GDI): A Power efficient method for digital combinational circuits,” IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 10 , no. 5 ,pp. 566 - 581 , 2002.
[2] N. Weste and D. Harris, CMOS VLSI Design: A Circuits and System Perspective, 3rd ed. Reading, MA, USA: Addison-Wesley May 2004.
[3] H.-.M. Lam and C.-Y. Tsui, “A MUX-based high-performance single-cycle CMOS comparator,” IEEE Transaction on Circuits System II, vol.54, no.7, pp.591-595, 2007.
[4] Sharma. A, Sharma. P, “Area and power efficient 4-bit comparator design by using 1-bit full adder module,” IEEE conference on Parallel, Distributed and Grid Computing, pp. 1-6, 2014.
[5] Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari, “Comparative performance analysis of XOR/XNOR function based high-speed CMOS full adder circuits for low voltage VLSI design,” International Journal of VLSI Design & Communication System,vol.3, no.2, pp. 221-242, 2012.