Search results for: FieldProgrammable Gate Array (FPGA)

Authors: S. Pradittara, M. Uthansakul, P. Uthansakul

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A concept of switched beam antennas consisting of 2×2 rectangular array spaced by λ/4 accompanied with a null locating has been proposed in the previous work. In this letter, the performance evaluations of its prototype are presented. The benefits of using proposed system have been clearly measured in term of signal quality, throughput and delays. Also, the impact of position shift which mesh router is not located on the expected beam direction has also been investigated.

Keywords: Antenna array, Beamforming, Null steering, WMNs.

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Authors: Shobha Sharma, Amita Dev

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This research paper presents highly optimized barrel shifter at 22nm Hi K metal gate strained Si technology node. This barrel shifter is having a unique combination of static and dynamic body bias which gives lowest power delay product. This power delay product is compared with the same circuit at same technology node with static forward biasing at ‘supply/2’ and also with normal reverse substrate biasing and still found to be the lowest. The power delay product of this barrel sifter is .39362X10-17J and is lowered by approximately 78% to reference proposed barrel shifter at 32nm bulk CMOS technology. Power delay product of barrel shifter at 22nm Hi K Metal gate technology with normal reverse substrate bias is 2.97186933X10-17J and can be compared with this design’s PDP of .39362X10-17J. This design uses both static and dynamic substrate biasing and also has approximately 96% lower power delay product compared to only forward body biased at half of supply voltage. The NMOS model used are predictive technology models of Arizona state university and the simulations to be carried out using HSPICE simulator.

Keywords: Dynamic body biasing, highly optimized barrel shifter, PDP, Static body biasing.

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Authors: Farid Moshgelani, Dhamin Al-Khalili, Côme Rozon

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In this paper, FinFET devices are analyzed with emphasis on sub-threshold leakage current control. This is achieved through proper biasing of the back gate, and through the use of asymmetric work functions for the four terminal FinFET devices. We are also examining different configurations of multiplexers and XOR gates using transistors of symmetric and asymmetric work functions. Based on extensive characterization data for MUX circuits, our proposed configuration using symmetric devices lead to leakage current and delay improvements of 65% and 47% respectively compared to results in the literature. For XOR gates, a 90% improvement in the average leakage current is achieved by using asymmetric devices. All simulations are based on a 25nm FinFET technology using the University of Florida UFDG model.

Keywords: FinFET, logic functions, asymmetric workfunction devices, back gate biasing, sub-threshold leakage current.

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Authors: Nurbanu Guzey, S. Jagannathan

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Locating Radio Controlled (RC) devices using their unintended emissions has a great interest considering security concerns. Weak nature of these emissions requires near field localization approach since it is hard to detect these signals in far field region of array. Instead of only angle estimation, near field localization also requires range estimation of the source which makes this method more complicated than far field models. Challenges of locating such devices in a near field region and real time environment are analyzed in this paper. An ESPRIT like near field localization scheme is utilized for both angle and range estimation. 1-D search with symmetric subarrays is provided. Two 7 element uniform linear antenna arrays (ULA) are employed for locating RC source. Experiment results of location estimation for one unintended emitting walkie-talkie for different positions are given.

Keywords: Localization, angle of arrival (AoA), range estimation, array signal processing, ESPRIT, uniform linear array (ULA).

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Authors: Tomyslav Sledevič, Artūras Serackis, Gintautas Tamulevičius, Dalius Navakauskas

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Paper presents an comparative evaluation of features extraction algorithm for a real-time isolated word recognition system based on FPGA. The Mel-frequency cepstral, linear frequency cepstral, linear predictive and their cepstral coefficients were implemented in hardware/software design. The proposed system was investigated in speaker dependent mode for 100 different Lithuanian words. The robustness of features extraction algorithms was tested recognizing the speech records at different signal to noise rates. The experiments on clean records show highest accuracy for Mel-frequency cepstral and linear frequency cepstral coefficients. For records with 15 dB signal to noise rate the linear predictive cepstral coefficients gives best result. The hard and soft part of the system is clocked on 50 MHz and 100 MHz accordingly. For the classification purpose the pipelined dynamic time warping core was implemented. The proposed word recognition system satisfy the real-time requirements and is suitable for applications in embedded systems.

Keywords: Isolated word recognition, features extraction, MFCC, LFCC, LPCC, LPC, FPGA, DTW.

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Authors: Kenji Suyama, Masahiro Oshida, Noboru Owada

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In this paper, an estimation accuracy of multiple moving talker tracking using a microphone array is improved. The tracking can be achieved by the adaptive method in which two algorithms are integrated, namely, the PAST (Projection Approximation Subspace Tracking) algorithm and the IPLS (Interior Point Least Square) algorithm. When either talker begins to speak again after a silent period, an appropriate feasible region for an evaluation function of the IPLS algorithm might not be set. Then, the tracking fails due to the incorrect updating. Therefore, if an increment of the number of active talkers is detected, the feasible region must be reset. Then, a low cost realization is required for the high speed tracking and a high accuracy realization is desired for the precise tracking. In this paper, the directions roughly estimated using the delayed-sum-array method are used for the resetting. Several results of experiments performed in an actual room environment show the effectiveness of the proposed method.

Keywords: moving talkers tracking, microphone array, signal subspace

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Authors: Chiang-Ho Cheng, Hong-Yih Cheng, An-Shik Yang, Tung-Hsun Hsu

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This paper reports a novel actuating design that uses the shear deformation of a piezoelectric actuator to deflect a bulge-diaphragm for driving an array microdroplet ejector. In essence, we employed a circular-shaped actuator poled radial direction with remnant polarization normal to the actuating electric field for inducing the piezoelectric shear effect. The array microdroplet ejector consists of a shear type piezoelectric actuator, a vibration plate, two chamber plates, two channel plates and a nozzle plate. The vibration, chamber and nozzle plate components are fabricated using nickel electroforming technology, whereas the channel plate is fabricated by etching of stainless steel. The diaphragm displacement was measured by the laser two-dimensional scanning vibrometer. The ejected droplets of the microejector were also observed via an optic visualization system.

Keywords: Actuator, nozzle, microejector, piezoelectric.

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Authors: M. M. Karkhanehchi, A. Ammani

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A simple analytical model has been developed to optimize biasing conditions for obtaining maximum linearity among lattice-matched, pseudomorphic and metamorphic HEMT types as well as enhancement and depletion HEMT modes. A nonlinear current-voltage model has been simulated based on extracted data to study and select the most appropriate type and mode of HEMT in terms of a given gate-source biasing voltage within the device so as to employ the circuit for the highest possible output current or voltage linear swing. Simulation results can be used as a basis for the selection of optimum gate-source biasing voltage for a given type and mode of HEMT with regard to a circuit design. The consequences can also be a criterion for choosing the optimum type or mode of HEMT for a predetermined biasing condition.

Keywords: Biasing, characteristic, linearity, simulation.

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Authors: Lei Qi, Rongxin Yan, Lichen Sun

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With the increasing of human space activities, the number of space debris has increased dramatically, and the possibility that spacecrafts on orbit are impacted by space debris is growing. A method is of the vital significance to real-time detect and assess spacecraft damage, determine of gas leak accurately, guarantee the life safety of the astronaut effectively. In this paper, acoustic sensor array is used to detect the acoustic signal which emits from the damage of the spacecraft on orbit. Then, we apply the time difference of arrival and beam forming algorithm to locate the damage and leakage. Finally, the extent of the spacecraft damage is evaluated according to the nonlinear ultrasonic method. The result shows that this method can detect the debris impact and the structural damage, locate the damage position, and identify the damage degree effectively. This method can meet the needs of structural damage detection for the spacecraft in-orbit.

Keywords: Acoustic sensor array, spacecraft, damage assessment, leakage location.

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Authors: Y. Bai, M. Bodlak, V. Frolov, S. Huber, V. Jary, I. Konorov, D. Levit, J. Novy, D. Steffen, O. Subrt, M. Virius

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Modern experiments in high energy physics impose great demands on the reliability, the efficiency, and the data rate of Data Acquisition Systems (DAQ). This contribution focuses on the development and deployment of the new communication library DIALOG for the intelligent, FPGA-based Data Acquisition System (iFDAQ) of the COMPASS experiment at CERN. The iFDAQ utilizing a hardware event builder is designed to be able to readout data at the maximum rate of the experiment. The DIALOG library is a communication system both for distributed and mixed environments, it provides a network transparent inter-process communication layer. Using the high-performance and modern C++ framework Qt and its Qt Network API, the DIALOG library presents an alternative to the previously used DIM library. The DIALOG library was fully incorporated to all processes in the iFDAQ during the run 2016. From the software point of view, it might be considered as a significant improvement of iFDAQ in comparison with the previous run. To extend the possibilities of debugging, the online monitoring of communication among processes via DIALOG GUI is a desirable feature. In the paper, we present the DIALOG library from several insights and discuss it in a detailed way. Moreover, the efficiency measurement and comparison with the DIM library with respect to the iFDAQ requirements is provided.

Keywords: Data acquisition system, DIALOG library, DIM library, FPGA, Qt framework, TCP/IP.

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Authors: Amira Abbes Kheriji, Faouzi Bouani, Mekki Ksouri, Mohamed Ben Ahmed

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Model Predictive Control (MPC) is increasingly being proposed for real time applications and embedded systems. However comparing to PID controller, the implementation of the MPC in miniaturized devices like Field Programmable Gate Arrays (FPGA) and microcontrollers has historically been very small scale due to its complexity in implementation and its computation time requirement. At the same time, such embedded technologies have become an enabler for future manufacturing enterprises as well as a transformer of organizations and markets. Recently, advances in microelectronics and software allow such technique to be implemented in embedded systems. In this work, we take advantage of these recent advances in this area in the deployment of one of the most studied and applied control technique in the industrial engineering. In fact in this paper, we propose an efficient framework for implementation of Generalized Predictive Control (GPC) in the performed STM32 microcontroller. The STM32 keil starter kit based on a JTAG interface and the STM32 board was used to implement the proposed GPC firmware. Besides the GPC, the PID anti windup algorithm was also implemented using Keil development tools designed for ARM processor-based microcontroller devices and working with C/Cµ langage. A performances comparison study was done between both firmwares. This performances study show good execution speed and low computational burden. These results encourage to develop simple predictive algorithms to be programmed in industrial standard hardware. The main features of the proposed framework are illustrated through two examples and compared with the anti windup PID controller.

Keywords: Embedded systems, Model Predictive Control, microcontroller, Keil tool.

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Authors: Spyridon Nikolaidis

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A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with the CCS technology. The model is parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. The transistor widths of the equivalent inverter are determined by HSPICE simulations and parametric expressions are developed for that using a fitting procedure. Results for the NAND gate shows that the proposed approach offers sufficient accuracy with an average error in propagation delay about 5%.

Keywords: CMOS gate modeling, Inverter modeling, transistor current model, timing model.

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Authors: Hai-Qing Xie, Yun Zeng, Yong-Hong Yan, Jian-Ping Zeng, Tai-Hong Wang

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Photo-BJMOSFET (Bipolar Junction Metal-Oxide- Semiconductor Field Effect Transistor) fabricated on SOI film was proposed. ITO film is adopted in the device as gate electrode to reduce light absorption. Depletion region but not inversion region is formed in film by applying gate voltage (but low reverse voltage) to achieve high photo-to-dark-current ratio. Comparisons of photoelectriccharacteristics executed among VGK=0V, 0.3V, 0.6V, 0.9V and 1.0V (reverse voltage VAK is equal to 1.0V for total area of 10×10μm2). The results indicate that the greatest improvement in photo-to-dark-current ratio is achieved up to 2.38 at VGK=0.6V. In addition, photo-BJMOSFET is compatible with CMOS integration due to big input resistance

Keywords: Photo-BJMOSFET, Responsivity, Sensitivity, Spectral response.

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Authors: Ko-Shao Chen, Yun Tsao, Chia-Hsuan Tsen, Chien-Chung Chen, Shu-Chuan Liao

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Electrospun microtube array membranes (MTAMs) made of PLLA (poly-L-lactic acid) have wide potential applications in tissue engineering. However, their surface hydrophobicity and poor biocompatability have limited their further usage. In this study, the surface of PLLA MTAMs were made hydrophilic by introducing extra functional groups, such as peroxide, via an acetic acid plasma (AAP). UV-graft polymerization of acrylic acid (G-AAc) was then used to produce carboxyl group on MTAMs surface, which bonded covalently with chitosan through EDC / NHS crosslinking agents. To evaluate the effects of the surface modification on PLLA MTAMs, water contact angle (WCA) measurement and cell compatibility tests were carried out. We found that AAP treated electrospun PLLA MTAMs grafted with AAc and, finally, with chitosan immobilized via crosslinking agent, exhibited improved hydrophilic and cell compatibility.

Keywords: Plasma, EDC/NHS, UV grafting, chitosan, microtube array membrane.

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Authors: N. Massoum, A. Guen. Bouazza, B. Bouazza, A. El Ouchdi

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The progress of industry integrated circuits in recent years has been pushed by continuous miniaturization of transistors. With the reduction of dimensions of components at 0.1 micron and below, new physical effects come into play as the standard simulators of two dimensions (2D) do not consider. In fact the third dimension comes into play because the transverse and longitudinal dimensions of the components are of the same order of magnitude. To describe the operation of such components with greater fidelity, we must refine simulation tools and adapted to take into account these phenomena. After an analytical study of the static characteristics of the component, according to the different operating modes, a numerical simulation is performed of field-effect transistor with submicron gate MESFET GaInP. The influence of the dimensions of the gate length is studied. The results are used to determine the optimal geometric and physical parameters of the component for their specific applications and uses.

Keywords: Monte Carlo simulation, transient electron transport, MESFET device.

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Authors: P. Subha Karuvelam, M. Rajaram

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Brushless DC motors (BLDC) are widely used in industrial areas. The BLDC motors are driven either by indirect ACAC converters or by direct AC-AC converters. Direct AC-AC converters i.e. matrix converters are used in this paper to drive the three phase BLDC motor and it eliminates the bulky DC link energy storage element. A matrix converter converts the AC power supply to an AC voltage of variable amplitude and variable frequency. A control technique is designed to generate the switching pulses for the three phase matrix converter. For the control of speed of the BLDC motor a separate PI controller and Fuzzy Logic Controller (FLC) are designed and a hysteresis current controller is also designed for the control of motor torque. The control schemes are designed and tested separately. The simulation results of both the schemes are compared and contrasted in this paper. The results show that the fuzzy logic control scheme outperforms the PI control scheme in terms of dynamic performance of the BLDC motor. Simulation results are validated with the experimental results.

Keywords: Fuzzy logic controller, matrix converter, permanent magnet brushless DC motor, PI controller.

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Authors: Cheng-Hsien Chang, Jyi-Tsong Lin, Po-Hsieh Lin, Hung-Pei Hsu, Chan-Hsiang Chang, Ming-Tsung Shih, Shih-Chuan Tseng, Min-Yan Lin

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In this paper, we have proposed a novel FinFET with extended body under the poly gate, which is called EB-FinFET, and its characteristic is demonstrated by using three-dimensional (3-D) numerical simulation. We have analyzed and compared it with conventional FinFET. The extended body height dependence on the drain induced barrier lowering (DIBL) and subthreshold swing (S.S) have been also investigated. According to the 3-D numerical simulation, the proposed structure has a firm structure, an acceptable short channel effect (SCE), a reduced series resistance, an increased on state drain current (I on) and a large normalized I DS. Furthermore, the structure can also improve corner effect and reduce self-heating effect due to the extended body. Our results show that the EBFinFET is excellent for nanoscale device.

Keywords: SOI, FinFET, tri-gate, self-heating effect.

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Authors: K. E. Kaharudin, A. H. Hamidon, F. Salehuddin

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Vertical Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is believed to suppress various short channel effect problems. The gate to channel coupling in vertical DG-MOSFET are doubled, thus resulting in higher current density. By having two gates, both gates are able to control the channel from both sides and possess better electrostatic control over the channel. In order to ensure that the transistor possess a superb turn-off characteristic, the subs-threshold swing (SS) must be kept at minimum value (60-90mV/dec). By utilizing SILVACO TCAD software, an n-channel vertical DG-MOSFET was successfully designed while keeping the sub-threshold swing (SS) value as minimum as possible. From the observation made, the value of sub-threshold swing (SS) was able to be varied by adjusting the height of the silicon pillar. The minimum value of sub-threshold swing (SS) was found to be 64.7mV/dec with threshold voltage (V_TH) of 0.895V. The ideal height of the vertical DG-MOSFET pillar was found to be at 0.265 µm.

Keywords: DG-MOSFET, pillar, SCE, vertical

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Authors: Najiya Omar, Hamed Aly, Timothy Little

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The optimal size of a photovoltaic (PV) array is considered a critical factor in designing an efficient PV system due to the dependence of the PV cell performance on temperature. A high temperature can lead to voltage losses of solar panels, whereas a low temperature can cause voltage overproduction. There are two possible scenarios of the inverter’s operation in which they are associated with the erroneous calculations of the number of PV panels: 1) If the number of the panels is scant and the temperature is high, the minimum voltage required to operate the inverter will not be reached. As a result, the inverter will shut down. 2) Comparably, if the number of panels is excessive and the temperature is low, the produced voltage will be more than the maximum limit of the inverter which can cause the inverter to get disconnected or even damaged. This article aims to assess theoretical and practical methodologies to calculate size and determine the topology of a PV array. The results are validated by applying an experimental evaluation for a 100 kW Grid-connected PV system for a location in Halifax, Nova Scotia and achieving a satisfactory system performance compared to the previous work done.

Keywords: Sizing PV panels, grid-connected PV, topology of PV array, theoretical and practical methodologies.

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Authors: Ajay Kushwaha, Hemen Kalita, M. Aslam

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Post growth annealing of solution grown ZnO nanowire array is performed under controlled oxygen ambience. The role of annealing over surface defects and their consequence on dark/photo-conductivity and photosensitivity of nanowire array is investigated. Surface defect properties are explored using various measurement tools such as contact angle, photoluminescence, Raman spectroscopy and XPS measurements. The contact angle of the NW films reduces due to oxygen annealing and nanowire film surface changes from hydrophobic (96°) to hydrophilic (16°). Raman and XPS spectroscopy reveal that oxygen annealing improves the crystal quality of the nanowire films. The defect band emission intensity (relative to band edge emission, ID/IUV) reduces from 1.3 to 0.2 after annealing at 600 °C at 10 SCCM flow of oxygen. An order enhancement in dark conductivity is observed in O2 annealed samples, while photoconductivity is found to be slightly reduced due to lower concentration of surface related oxygen defects.

Keywords: Zinc Oxide, Surface defects, Photoluminescence, Photoconductivity, Photosensor and Nanowire thin film.

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Authors: Hung-Pei Hsu, Jyi-Tsong Lin, Po-Hsieh Lin, Cheng-Hsien Chang, Ming-Tsung Shih, Chan-Hsiang Chang, Shih-Chuan Tseng, Min-Yan Lin, Shih-Wen Hsu

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In this paper, we propose a novel metal oxide semiconductor field effect transistor with L-shaped channel structure (LMOS), and several type of L-shaped structures are also designed, studied and compared with the conventional MOSFET device for the same average gate length (Lavg). The proposed device electrical characteristics are analyzed and evaluated by three dimension (3-D) ISE-TCAD simulator. It can be confirmed that the LMOS devices have higher on-state drain current and both lower drain-induced barrier lowering (DIBL) and subthreshold swing (S.S.) than its conventional counterpart has. In addition, the transconductance and voltage gain properties of the LMOS are also improved.

Keywords: Average gate length (Lavg), drain-induced barrier lowering (DIBL), L-shaped channel MOSFET (LMOS), subthreshold swing (S.S.).

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Authors: Sachin Kamble, Shradha Gawankar

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This paper presents the findings of successful implementation of Business Process Reengineering (BPR) of cement dispatch activities in a cement manufacturing plant located in India. Simulation model was developed for the purpose of identifying and analyzing the areas for improvement. The company was facing a problem of low throughput rate and subsequent forced stoppages of the plant leading to a high production loss of 15000MT per month. It was found from the study that the present systems and procedures related to the in-plant logistics plant required significant changes. The major recommendations included process improvement at the entry gate, reducing the cycle time at the security gate and installation of an additional weigh bridge. This paper demonstrates how BPR can be implemented for improving the in-plant logistics process. Various recommendations helped the plant to increase its throughput by 14%.

Keywords: Business process reengineering, simulation modeling, in-plant logistics, distribution process, cement industry.

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Authors: S. Praveen, P. Sojan Lal

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Obfuscation is a low cost software protection methodology to avoid reverse engineering and re engineering of applications. Source code obfuscation aims in obscuring the source code to hide the functionality of the codes. This paper proposes an Array data transformation in order to obfuscate the source code which uses arrays. The applications using the proposed data structures force the programmer to obscure the logic manually. It makes the developed obscured codes hard to reverse engineer and also protects the functionality of the codes.

Keywords: Reverse Engineering, Source Code Obfuscation.

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Authors: C. Kalamani, V. Abishek Karthick, S. Anitha, K. Kavin Kumar

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The fault tolerant system plays a crucial role in the critical applications which are being used in the present scenario. A fault may change the functionality of circuits. Aim of this paper is to design multiplier using fault tolerant hybrid full adder. Fault tolerant hybrid full adder is designed to check and repair any fault in the circuit using self-checking circuit and the self-repairing circuit. Further, the use of conventional logic circuits may result in more area, delay as well as power consumption. In order to reduce these parameters of the circuit, GDI (Gate Diffusion Input) techniques with less number of transistors are used compared to conventional full adder circuit. This reduces the area, delay and power consumption. The proposed method solves the major problems occurring in the most crucial and critical applications.

Keywords: Gate diffusion input, hybrid full adder, self-checking, fault tolerant.

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Authors: Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis

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Modern applications realized onto FPGAs exhibit high connectivity demands. Throughout this paper we study the routing constraints of Virtex devices and we propose a systematic methodology for designing a novel general-purpose interconnection network targeting to reconfigurable architectures. This network consists of multiple segment wires and SB patterns, appropriately selected and assigned across the device. The goal of our proposed methodology is to maximize the hardware utilization of fabricated routing resources. The derived interconnection scheme is integrated on a Virtex style FPGA. This device is characterized both for its high-performance, as well as for its low-energy requirements. Due to this, the design criterion that guides our architecture selections was the minimal Energy×Delay Product (EDP). The methodology is fully-supported by three new software tools, which belong to MEANDER Design Framework. Using a typical set of MCNC benchmarks, extensive comparison study in terms of several critical parameters proves the effectiveness of the derived interconnection network. More specifically, we achieve average Energy×Delay Product reduction by 63%, performance increase by 26%, reduction in leakage power by 21%, reduction in total energy consumption by 11%, at the expense of increase of channel width by 20%.

Keywords: Design Methodology, FPGA, Interconnection, Low-Energy, High-Performance, CAD tool.

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Authors: Ala'eddin A. Saif , Z. A. Z. Jamal, Z. Sauli, P. Poopalan

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The ferroelectric behavior of barium strontium titanate (BST) in thin film form has been investigated in order to study the possibility of using BST for ferroelectric gate-field effect transistor (FeFET) for memory devices application. BST thin films have been fabricated as Al/BST/Pt/SiO2/Si-gate configuration. The variation of the dielectric constant (ε) and tan δ with frequency have been studied to ensure the dielectric quality of the material. The results show that at low frequencies, ε increases as the Ba content increases, whereas at high frequencies, it shows the opposite variation, which is attributed to the dipole dynamics. tan δ shows low values with a peak at the mid-frequency range. The ferroelectric behavior of the Al/BST/Pt/SiO2/Si has been investigated using C-V characteristics. The results show that the strength of the ferroelectric hysteresis loop increases as the Ba content increases; this is attributed to the grain size and dipole dynamics effect.

Keywords: BST thin film, Electrical properties, Ferroelectrichysteresis, Ferroelectric FET.

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Authors: David M. Lucas, Charles W. Jarrett

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In the culture of Thailand, the Yak serve as a mediated icon representing strength, power, and mystical protection not only for the Buddha, but for population of worshipers. Originating from the forests of China, the Yak continues to stand guard at the gates of Buddhist temples. The Yak represents Thai culture in the hearts of Thai people. This paper presents a qualitative study regarding the curious mix of media, culture, and religion that projects the Yak of Thailand as a larger than life message throughout the political, cultural, and religious spheres. The gate guardians, or gods as they are sometimes called, appear throughout the religious temples of Asian cultures. However, the Asian cultures demonstrate differences in artistic renditions (or presentations) of such sentinels. Thailand gate guards (the Yak) stand in front of many Buddhist temples, and these iconic figures display unique features with varied symbolic significance. The temple (or wat), plays a vital role in every community; and, for many people, Thailand’s temples are the country’s most endearing sights. The authors applied folknography as a methodology to illustrate the importance of the Thai Yak in serving as meaningful icons that transcend not only time, but the culture, religion, and mass media. The Yak represents mythical, religious, artistic, cultural, and militaristic significance for the Thai people. Data collection included interviews, focus groups, and natural observations. This paper summarizes the perceptions of the Thai people concerning their gate sentries and the relationship, communication, connection, and the enduring respect that Thai people hold for their guardians of the gates.

Keywords: Communication, Culture, Folknography, Icon, Image, Media, Protection, Religion, Yak.

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Authors: Chi-Fang Huang, Xi-Zhang Lin, Yi-Ru Yang

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Aiming the application of localized hyperthermia, a magnetic induction system with new approaches is proposed. The techniques in this system for improving the effectiveness of localized hyperthermia are that using magnetic circuit and the multiple-coil array instead of a giant coil for generating magnetic field. Specially, amorphous metal is adopted as the material of magnetic circuit. Detail design parameters of hardware are well described. Simulation tool is employed for this work and experiment result is reported as well.

Keywords: cancer therapy, hyperthermia, Helmholtz coil, induction heating, magnetic circuit.

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Authors: Padmanabhan Balasubramanian, Ryuta Arisaka

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Factoring Boolean functions is one of the basic operations in algorithmic logic synthesis. A novel algebraic factorization heuristic for single-output combinatorial logic functions is presented in this paper and is developed based on the set theory paradigm. The impact of factoring is analyzed mainly from a low power design perspective for standard cell based digital designs in this paper. The physical implementation of a number of MCNC/IWLS combinational benchmark functions and sub-functions are compared before and after factoring, based on a simple technology mapping procedure utilizing only standard gate primitives (readily available as standard cells in a technology library) and not cells corresponding to optimized complex logic. The power results were obtained at the gate-level by means of an industry-standard power analysis tool from Synopsys, targeting a 130nm (0.13μm) UMC CMOS library, for the typical case. The wire-loads were inserted automatically and the simulations were performed with maximum input activity. The gate-level simulations demonstrate the advantage of the proposed factoring technique in comparison with other existing methods from a low power perspective, for arbitrary examples. Though the benchmarks experimentation reports mixed results, the mean savings in total power and dynamic power for the factored solution over a non-factored solution were 6.11% and 5.85% respectively. In terms of leakage power, the average savings for the factored forms was significant to the tune of 23.48%. The factored solution is expected to better its non-factored counterpart in terms of the power-delay product as it is well-known that factoring, in general, yields a delay-efficient multi-level solution.

Keywords: Factorization, Set theory, Logic function, Standardcell based design, Low power.

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Authors: Mei Shan Ngan, Chee Wei Tan

Abstract:

Due to the non-linear characteristics of photovoltaic (PV) array, PV systems typically are equipped with the capability of maximum power point tracking (MPPT) feature. Moreover, in the case of PV array under partially shaded conditions, hotspot problem will occur which could damage the PV cells. Partial shading causes multiple peaks in the P-V characteristic curves. This paper presents a hybrid algorithm of Particle Swarm Optimization (PSO) and Artificial Neural Network (ANN) MPPT algorithm for the detection of global peak among the multiple peaks in order to extract the true maximum energy from PV panel. The PV system consists of PV array, dc-dc boost converter controlled by the proposed MPPT algorithm and a resistive load. The system was simulated using MATLAB/Simulink package. The simulation results show that the proposed algorithm performs well to detect the true global peak power. The results of the simulations are analyzed and discussed.

Keywords: Photovoltaic (PV), Partial Shading, Maximum Power Point Tracking (MPPT), Particle Swarm Optimization (PSO) and Artificial Neural Network (ANN)

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