Search results for: double gate PN diode based tunnel field effect transistor

Authors: Ahmed Shariful Alam, Abu Hena M. Mustafa Kamal, M. Abdul Rahman, M. Nasmus Sakib Khan Shabbir, Atiqul Islam

Abstract:

According to the rules of quantum mechanics there is a non-vanishing probability of for an electron to tunnel through a thin insulating barrier or a thin capacitor which is not possible according to the laws of classical physics. Tunneling of electron through a thin insulating barrier or tunnel junction is a random event and the magnitude of current flowing due to the tunneling of electron is very low. As the current flowing through a Single Electron Transistor (SET) is the result of electron tunneling through tunnel junctions of its source and drain the supply voltage requirement is also very low. As a result, the power consumption across a Single Electron Transistor is ultra-low in comparison to that of a MOSFET. In this paper simulations have been done with PSPICE for an inverter built with both SETs and MOSFETs. 35mV supply voltage was used for a SET built inverter circuit and the supply voltage used for a CMOS inverter was 3.5V.

Keywords: ITRS, enhancement type MOSFET, island, DC analysis, transient analysis, power consumption, background charge co-tunneling.

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Authors: K. Karami, S. Hassan, S. Taking, A. Ofiare, A. Dhongde, A. Al-Khalidi, E. Wasige

Abstract:

We have made a comparative study on the influence of Al2O3 and HfO2 grown using Atomic Layer Deposition (ALD) technique as dielectric in the AlGaN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) structure. Five samples consisting of 20 nm and 10 nm each of A2lO3 and HfO2 respectively and a Schottky gate HEMT, were fabricated and measured. The threshold voltage shifts towards negative by 0.1 V and 1.8 V for 10 nm thick HfO2 and 10 nm thick Al2O3 gate dielectric layers, respectively. The negative shift for the 20 nm HfO2 and 20 nm Al2O3 were 1.2 V and 4.9 V, respectively. Higher gm/IDS (transconductance to drain current) ratio was also obtained in HfO2 than Al2O3. With both materials as dielectric, a significant reduction in the gate leakage current in the order of 104 was obtained compared to the sample without the dielectric material.

Keywords: AlGaN/GaN HEMTs, Al2O3, HfO2, MOSHEMTs.

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Authors: Hung-Pei Hsu, Jyi-Tsong Lin, Po-Hsieh Lin, Cheng-Hsien Chang, Ming-Tsung Shih, Chan-Hsiang Chang, Shih-Chuan Tseng, Min-Yan Lin, Shih-Wen Hsu

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In this paper, we propose a novel metal oxide semiconductor field effect transistor with L-shaped channel structure (LMOS), and several type of L-shaped structures are also designed, studied and compared with the conventional MOSFET device for the same average gate length (Lavg). The proposed device electrical characteristics are analyzed and evaluated by three dimension (3-D) ISE-TCAD simulator. It can be confirmed that the LMOS devices have higher on-state drain current and both lower drain-induced barrier lowering (DIBL) and subthreshold swing (S.S.) than its conventional counterpart has. In addition, the transconductance and voltage gain properties of the LMOS are also improved.

Keywords: Average gate length (Lavg), drain-induced barrier lowering (DIBL), L-shaped channel MOSFET (LMOS), subthreshold swing (S.S.).

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Authors: K. Maria Agnes, J. Joshua Bapu

Abstract:

This paper impart the design and testing of Nanotechnology based sequential circuits using multiplexer conservative QCA (MX-CQCA) logic gates, which is easily testable using only two vectors. This method has great prospective in the design of sequential circuits based on reversible conservative logic gates and also smashes the sequential circuits implemented in traditional gates in terms of testability. Reversible circuits are similar to usual logic circuits except that they are built from reversible gates. Designs of multiplexer conservative QCA logic based two vectors testable double edge triggered (DET) sequential circuits in VHDL language are also accessible here; it will also diminish intricacy in testing side. Also other types of sequential circuits such as D, SR, JK latches are designed using this MX-CQCA logic gate. The objective behind the proposed design methodologies is to amalgamate arithmetic and logic functional units optimizing key metrics such as garbage outputs, delay, area and power. The projected MX-CQCA gate outshines other reversible gates in terms of the intricacy, delay.

Keywords: Conservative logic, Double edge triggered (DET) flip flop, majority voters, MX-CQCA gate, reversible logic, Quantum dot Cellular automata.

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Authors: Yun-Hsuan Yu, Chi-Shung Tang, Nzar Rauf Abdullah, Vidar Gudmundsson

Abstract:

Spin-orbit gap feature in energy dispersion of one-dimensional devices is revealed via strong spin-orbit interaction (SOI) effects under Zeeman field. We describe the utilization of a finger-gate or a top-gate to control the spin-dependent transport characteristics in the SOI-Zeeman influenced split-gate devices by means of a generalized spin-mixed propagation matrix method. For the finger-gate system, we find a bound state in continuum for incident electrons within the ultra-low energy regime. For the top-gate system, we observe more bound-state features in conductance associated with the formation of spin-associated hole-like or electron-like quasi-bound states around band thresholds, as well as hole bound states around the reverse point of the energy dispersion. We demonstrate that the spin-dependent transport behavior of a top-gate system is similar to that of a finger-gate system only if the top-gate length is less than the effective Fermi wavelength.

Keywords: Spin-orbit, Zeeman, top-gate, finger-gate, bound state.

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Authors: Chien-Yeh Hsu, Yuan-Ching Chiang, Zi-Jie Chien, Sih-Li Chen

Abstract:

In this study, a field experiment and performance analysis of air-tunnel heat exchanger integrated with water-filled raft foundation of residential building were performed. In order to obtain better performance, conventional applications of air-tunnel inevitably have high initial cost or issues about insufficient installation space. To improve the feasibility of air tunnel heat exchanger in high-density housing, an integrated system consisting of air pipes immersed in the water-filled raft foundation was presented, taking advantage of immense amount of water and relatively stable temperature in raft foundation of building. The foundation-integrated air tunnel was applied to a residential building located in Yilan, Taiwan, and its thermal performance was measured in the field experiment. The results indicated that the cooling potential of integrated system was close to the potential of soil-based EAHE at 2 m depth or deeper. An analytical model based on thermal resistance method was validated by measurement results, and was used to carry out the dimensioning of foundation-integrated air tunnel. The discrepancies between calculated value and measured data were less than 2.7%. In addition, the return-on-investment with regard to thermal performance and economics of the application was evaluated. Because the installation for air tunnel is scheduled in the building foundation construction, the utilization of integrated system spends less construction cost compare to the conventional earth-air tunnel.

Keywords: Air tunnel, ground heat exchanger, raft foundation, residential building.

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Authors: Yashvir Singh, Swati Chamoli

Abstract:

In this paper, a power laterally-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) on In_0.53Ga_0.47As is presented. The device utilizes a thicker field-oxide with low dielectric constant under the field-plate in order to achieve possible reduction in device capacitances and reduced-surface-field effect. Using 2D numerical simulations, performance of the proposed device is analyzed and compared with that of the conventional LDMOSFET. The proposed structure provides 50% increase in the breakdown voltage, 21% increase in transit frequency, and 72% improvement in figure-of-merit over the conventional device for same cell pitch.

Keywords: InGaAs, dielectric, lateral, power MOSFET.

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Authors: Hani Baek, Gwang Min Sun, Chansun Shin, Sung Ho Ahn

Abstract:

Fast neutron irradiation using nuclear reactors is an effective method to improve switching loss and short circuit durability of power semiconductor (insulated gate bipolar transistors (IGBT) and insulated gate transistors (IGT), etc.). However, not only fast neutrons but also thermal neutrons, epithermal neutrons and gamma exist in the nuclear reactor. And the electrical properties of the IGBT may be deteriorated by the irradiation of gamma. Gamma irradiation damages are known to be caused by Total Ionizing Dose (TID) effect and Single Event Effect (SEE), Displacement Damage. Especially, the TID effect deteriorated the electrical properties such as leakage current and threshold voltage of a power semiconductor. This work can confirm the effect of the gamma irradiation on the electrical properties of 600 V NPT-IGBT. Irradiation of gamma forms lattice defects in the gate oxide and Si-SiO₂ interface of the IGBT. It was confirmed that this lattice defect acts on the center of the trap and affects the threshold voltage, thereby negatively shifted the threshold voltage according to TID. In addition to the change in the carrier mobility, the conductivity modulation decreases in the n-drift region, indicating a negative influence that the forward voltage drop decreases. The turn-off delay time of the device before irradiation was 212 ns. Those of 2.5, 10, 30, 70 and 100 kRad(Si) were 225, 258, 311, 328, and 350 ns, respectively. The gamma irradiation increased the turn-off delay time of the IGBT by approximately 65%, and the switching characteristics deteriorated.

Keywords: NPT-IGBT, gamma irradiation, switching, turn-off delay time, recombination, trap center.

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Authors: M. Geetha Priya, K. Baskaran, S. Srinivasan

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Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.

Keywords: Low power, CMOS, pass-transistor, flash memory, logic gates.

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Authors: Srikanta Bose, S.K. Mazumder

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In the present simulation work, an attempt is made to study the switching dynamics of an optically controlled 4HSiC thyristor power semiconductor device with the use of GaAs optically triggered power transistor. The half-cell thyristor has the forward breakdown of 200 V and reverse breakdown of more than 1000 V. The optically controlled thyristor has a rise time of 0.14 μs and fall time of 0.065 μs. The turn-on and turn-off delays are 0.1 μs and 0.06 μs, respectively. In addition, this optically controlled thyristor is used as a control switch for the DC-DC Boost converter. The pn-diode used for the converter has the forward drop of 2.8 V and reverse breakdown of around 400 V.

Keywords: 4H-SiC, Boost converter, Optical triggering, Power semiconductor device, thyristor.

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Authors: Mehdi Saeidmanesh, Razali Ismail

Abstract:

Recently, Graphene Nanoribbon Field Effect Transistors (GNR FETs) attract a great deal of attention due to their better performance in comparison with conventional devices. In this paper, channel length Modulation (CLM) effect on the electrical characteristics of GNR FETs is analytically studied and modeled. To this end, the special distribution of the electric potential along the channel and current-voltage characteristic of the device is modeled. The obtained results of analytical model are compared to the experimental data of published works. As a result, it is observable that considering the effect of CLM, the current-voltage response of GNR FET is more realistic.

Keywords: Graphene nanoribbon, field effect transistors, short channel effects, channel length modulation.

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Authors: Rekha V. Dundur , M.V.Latte, S.Y. Kulkarni, M.K.Venkatesha

Abstract:

The advent of multi-million gate Field Programmable Gate Arrays (FPGAs) with hardware support for multiplication opens an opportunity to recreate a significant portion of the front end of a human cochlea using this technology. In this paper we describe the implementation of the cochlear filter and show that it is entirely suited to a single device XC3S500 FPGA implementation .The filter gave a good fit to real time data with efficiency of hardware usage.

Keywords: Cochlea, FPGA, IIR (Infinite Impulse Response), Multiplier.

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Authors: Ashwani K. Rana, Narottam Chand, Vinod Kapoor

Abstract:

This paper presents a new compact analytical model of the gate leakage current in high-k based nano scale MOSFET by assuming a two-step inelastic trap-assisted tunneling (ITAT) process as the conduction mechanism. This model is based on an inelastic trap-assisted tunneling (ITAT) mechanism combined with a semiempirical gate leakage current formulation in the BSIM 4 model. The gate tunneling currents have been calculated as a function of gate voltage for different gate dielectrics structures such as HfO2, Al2O3 and Si3N4 with EOT (equivalent oxide thickness) of 1.0 nm. The proposed model is compared and contrasted with santaurus simulation results to verify the accuracy of the model and excellent agreement is found between the analytical and simulated data. It is observed that proposed analytical model is suitable for different highk gate dielectrics simply by adjusting two fitting parameters. It was also shown that gate leakages reduced with the introduction of high-k gate dielectric in place of SiO2.

Keywords: Analytical model, High-k gate dielectrics, inelastic trap assisted tunneling, metal–oxide–semiconductor (MOS) devices.

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand Tan Kong Yew

Abstract:

This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), and ion sensor electronics.

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand, Tan Kong Yew

Abstract:

This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 Rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics.

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Authors: Hongjun Liu, Cunxiao Gao, Jintao Tao, Wei Zhao, Yishan Wang

Abstract:

A compact tunable 10 W picosecond source based on Yb-doped fiber amplification of gain switch laser diode has been demonstrated. A gain switch semiconductor laser diode was used as the seed source, and a multi-stage single mode Yb-doped fiber preamplifier was combined with two large mode area double-clad Yb-doped fiber main amplifiers to construct the amplification system. The tunable pulses with high stability and excellent beam quality (M2<1.2) of 10 W average power 150 ps pulse duration at 1 MHz repetition rate were obtained. The central wavelength with the line width of 2.5-3 nm was tunable from 1053 nm to 1073 nm.

Keywords: Fiber laser, fiber amplifier, picosecond laser, highpower laser

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Authors: Ashwani K. Rana, Narottam Chand, Vinod Kapoor

Abstract:

In this paper, gate leakage current has been mitigated by the use of novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure for the first time. A compact analytical model has been developed to study the gate leakage behaviour of proposed MOSFET structure. The result obtained has found good agreement with the Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.

Keywords: Gate tunneling current, analytical model, spacer dielectrics, DIBL, subthreshold slope.

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Authors: Fasil Endalamaw

Abstract:

Digital magnitude comparators based on Gate Diffusion Input (GDI) implementation technique are high speed and area-efficient, and they consume less power as compared to other implementation techniques. However, they are less efficient for some logic gates and have no full voltage swing. In this paper, we made a performance comparison between the GDI implementation technique and other implementation methods, such as Static CMOS, Pass Transistor Logic (PTL), and Transmission Gate (TG) in 90 nm, 120 nm, and 180 nm CMOS technologies using BSIM4 MOS model. We proposed a methodology (hybrid implementation) of implementing digital magnitude comparators which significantly improved the power, speed, area, and voltage swing requirements. Simulation results revealed that the hybrid implementation of digital magnitude comparators show a 10.84% (power dissipation), 41.6% (propagation delay), 47.95% (power-delay product (PDP)) improvement compared to the usual GDI implementation method. We used Microwind & Dsch Version 3.5 as well as the Tanner EDA 16.0 tools for simulation purposes.

Keywords: Efficient, gate diffusion input, high speed, low power, CMOS.

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Authors: Akash Rathee, Harish Parthasarathy

Abstract:

In this paper, a frequency-variation based method has been proposed for transistor parameter estimation in a commonemitter transistor amplifier circuit. We design an algorithm to estimate the transistor parameters, based on noisy measurements of the output voltage when the input voltage is a sine wave of variable frequency and constant amplitude. The common emitter amplifier circuit has been modelled using the transistor Ebers-Moll equations and the perturbation technique has been used for separating the linear and nonlinear parts of the Ebers-Moll equations. This model of the amplifier has been used to determine the amplitude of the output sinusoid as a function of the frequency and the parameter vector. Then, applying the proposed method to the frequency components, the transistor parameters have been estimated. As compared to the conventional time-domain least squares method, the proposed method requires much less data storage and it results in more accurate parameter estimation, as it exploits the information in the time and frequency domain, simultaneously. The proposed method can be utilized for parameter estimation of an analog device in its operating range of frequencies, as it uses data collected from different frequencies output signals for parameter estimation.

Keywords: Perturbation Technique, Parameter estimation, frequency-variation based method.

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Authors: A. Kamath, Z. X. Chen, C. J. Gu, F. Zheng, X. P. Wang, N. Singh, G-Q. Lo

Abstract:

In this paper we use low frequency noise analysis to understand and map the current conduction path in a multi gate junctionless FinFET.  The device used in this study behaves as a gated resistor and shows excellent short channel effect suppression due to its multi gate structure. Generally for a bulk conduction device like the junctionless device studied in this work, the low frequency noise can be modelled using the mobility fluctuation model; however for this device we can also see the effect of carrier fluctuations on the LFN characteristic. The noise characteristic at different gate bias and also the possible location of the traps is explained.

Keywords: LFN analysis, junctionless, Current conduction path, FinFET.

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Authors: M. Azadi, M. Kalhor

Abstract:

Excavation of shallow tunnels such as subways in urban areas plays a significant role as a life line and investigation of the soil behavior against tunnel construction is one of the vital subjects studied in the geotechnical scope. Nowadays, urban tunnels are mostly drilled by T.B.Ms and changing the applied forces to tunnel lining is one of the most risky matters while drilling tunnels by these machines. Variation of soil cementation can change the behavior of these forces in the tunnel lining. Therefore, this article is designed to assess the impact of tunnel excavation in different soils and several amounts of cementation on applied loads to tunnel lining under static and dynamic loads. According to the obtained results, changing the cementation of soil will affect the applied loadings to the tunnel envelope significantly. It can be determined that axial force in tunnel lining decreases considerably when soil cementation increases. Also, bending moment and shear force in tunnel lining decreases as the soil cementation increases and causes bending and shear behavior of the segments to improve. Based on the dynamic analyses, as cohesion factor in soil increases, bending moment, axial and shear forces of segments decrease but lining behavior of the tunnel is the same as static state. The results show that decreasing the overburden applied to lining caused by cementation is different in two static and dynamic states.

Keywords: Tunnel, Soil cementation, Static, Dynamic.

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Authors: G. Renuka Devi

Abstract:

This paper analyzes the experimental investigation of indirect field oriented control of Field Programmable Gate Array (FPGA) based five-phase induction motor drive. A detailed d-q modeling and Space Vector Pulse Width Modulation (SVPWM) technique of 5-phase drive is elaborated in this paper. In the proposed work, the prototype model of 1 hp 5-phase Voltage Source Inverter (VSI) fed drive is implemented in hardware. SVPWM pulses are generated in FPGA platform through Very High Speed Integrated Circuit Hardware Description Language (VHDL) coding. The experimental results are observed under different loading conditions and compared with simulation results to validate the simulation model.

Keywords: Five-phase induction motor drive, field programmable gate array, indirect field oriented control, multi-phase, space vector pulse width modulation, voltage source inverter, very high speed integrated circuit hardware description language.

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Authors: S. A. Anuar, N. H. Hamid, M. H. Hashim, S. M. D. Salleh

Abstract:

This paper present the experimental work of double unit tunnel form building (TFB) subjected to in-plane lateral cyclic loading. A one third scale of 3-storey double unit of TFB is tested until its strength degradation. Then, the TFB is repaired and retrofitted using additional shear wall, steel angle and CFRP sheet. The crack patterns, lateral strength, stiffness, ductility and equivalent viscous damping (EVD) were analyzed and compared before and after repair and retrofit. The result indicates that the lateral strength increases by 22% in pushing and 27% in pulling direction. Moreover, the stiffness and ductility obtained before and after retrofit increase tremendously by 87.87% and 39.66%, respectively. Meanwhile, the energy absorption measured by equivalent viscous damping obtained after retrofit increase by 12.34% in pulling direction. It can be concluded that the proposed retrofit method is capable to increase the lateral strength capacity, stiffness and energy absorption of double unit TFB.

Keywords: Crack pattern, stiffness, ductility, equivalent viscous damping.

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Authors: Hadi Farhadian, Homayoon Katibeh

Abstract:

In this paper, groundwater seepage into Amirkabir tunnel has been estimated using analytical and numerical methods for 14 different sections of the tunnel. Site Groundwater Rating (SGR) method also has been performed for qualitative and quantitative classification of the tunnel sections. The obtained results of above mentioned methods were compared together. The study shows reasonable accordance with results of the all methods unless for two sections of tunnel. In these two sections there are some significant discrepancies between numerical and analytical results mainly originated from model geometry and high overburden. SGR and the analytical and numerical calculations, confirm high concentration of seepage inflow in fault zones. Maximum seepage flow into tunnel has been estimated 0.425 lit/sec/m using analytical method and 0.628 lit/sec/m using numerical method occured in crashed zone. Based on SGR method, six sections of 14 sections in Amirkabir tunnel axis are found to be in "No Risk" class that is supported by the analytical and numerical seepage value of less than 0.04 lit/sec/m.

Keywords: Water Seepage, Amirkabir Tunnel, Analytical Method, DEM, SGR.

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Authors: Hai-Qing Xie, Yun Zeng, Yong-Hong Yan, Guo-Liang Zhang, Tai-Hong Wang

Abstract:

We propose photo-BJMOSFET (Bipolar Junction Metal-Oxide-Semiconductor Field Effect Transistor) fabricated on SOI film. ITO film is adopted in the device as gate electrode to reduce light absorption. I-V characteristics of photo-BJMOSFET obtained in dark (dark current) and under 570nm illumination (photo current) are studied furthermore to achieve high photo-to-dark-current contrast ratio. Two variables in the calculation were the channel length and the thickness of the film which were set equal to six different values, i.e., L=2, 4, 6, 8, 10, and 12μm and three different values, i.e., dsi =100, 200 and 300nm, respectively. The results indicate that the greatest photo-to-dark-current contrast ratio is achieved with L=10μm and dsi=200 nm at VGK=0.6V.

Keywords: Photo-to-dark-current contrast ratio, Photo-current, Dark-current, Process parameter

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Authors: Seyed Abolhasan Naeini, Saeideh Mohammadi

Abstract:

Site response has a profound effect on earthquake damages. Seismic interaction of urban tunnels with surface structures could also affect seismic site response. Here, we use FLAC 2D to investigate the interaction of a single tunnel and twin tunnels-surface structures on the site response. Soil stratification and properties are selected based on Line. No 7 of the Tehran subway. The effect of surface structure is considered in two ways: Equivalent surcharge and geometrical modeling of the structure. Comparison of the results shows that consideration of the structure geometry is vital in dynamic analysis and leads to the changes in the magnitude of displacements, accelerations and response spectrum. Therefore it is necessary for the surface structures to be wholly modeled and not just considered as a surcharge in dynamic analysis. The use of twin tunnel also leads to the reduction of dynamic residual settlement.

Keywords: Superstructure, tunnel, site response, surcharge, interaction.

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Authors: Min-ju Kwon, Chae-won Kim, Jeong-yun Seo, Hee-guk Chae, Yong-seo Koo

Abstract:

In this paper, we presented the LDO (low-dropout) regulator which enhanced the PSRR by applying the constant current source generation technique through the BGR (Band Gap Reference) to form the noise sensing circuit. The current source through the BGR has a constant current value even if the applied voltage varies. Then, the noise sensing circuit, which is composed of the current source through the BGR, operated between the error amplifier and the pass transistor gate of the LDO regulator. As a result, the LDO regulator has a PSRR of -68.2 dB at 1k Hz, -45.85 dB at 1 MHz and -45 dB at 10 MHz. the other performance of the proposed LDO was maintained at the same level of the conventional LDO regulator.

Keywords: LDO regulator, noise sensing circuit, current reference, pass transistor.

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Authors: J. Šejnoha, D. Jarušková, O. Špačková, E. Novotná

Abstract:

Construction of tunnels is connected with high uncertainty in the field of costs, construction period, safety and impact on surroundings. Risk management became therefore a common part of tunnel projects, especially after a set of fatal collapses occurred in 1990's. Such collapses are caused usually by combination of factors that can be divided into three main groups, i.e. unfavourable geological conditions, failures in the design and planning or failures in the execution. This paper suggests a procedure enabling quantification of the excavation risk related to extraordinary accidents using FTA and ETA tools. It will elaborate on a common process of risk analysis and enable the transfer of information and experience between particular tunnel construction projects. Further, it gives a guide for designers, management and other participants, how to deal with risk of such accidents and how to make qualified decisions based on a probabilistic approach.

Keywords: risk quantification, tunnel collapse, ETA, FTA, geotechnical risk

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Authors: S. Boorboor, S. A. H. Feghhi, H. Jafari

Abstract:

The ionizing radiations cause different kinds of damages in electronic components. MOSFETs, most common transistors in today’s digital and analog circuits, are severely sensitive to TID damage. In this work, the threshold voltage shift of CD4007 device, which is an integrated circuit including P-channel and N-channel MOS transistors, was investigated for low dose gamma irradiation under different gate bias voltages. We used linear extrapolation method to extract threshold voltage from I_D-V_G characteristic curve. The results showed that the threshold voltage shift was approximately 27.5 mV/Gy for N-channel and 3.5 mV/Gy for P-channel transistors at the gate bias of |9 V| after irradiation by Co-60 gamma ray source. Although the sensitivity of the devices under test were strongly dependent to biasing condition and transistor type, the threshold voltage shifted linearly versus accumulated dose in all cases. The overall results show that the application of CD4007 as an electronic buffer in a radiation therapy system is limited by TID damage. However, this integrated circuit can be used as a cheap and sensitive radiation dosimeter for accumulated dose measurement in radiation therapy systems.

Keywords: Threshold voltage shift, MOS transistor, linear extrapolation, gamma irradiation.

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Authors: S.Aksoy, Y.Caglar

Abstract:

n-CdO/p-Si heterojunction diode was fabricated using sol-gel spin coating technique which is a low cost and easily scalable method for preparing of semiconductor films. The structural and morphological properties of CdO film were investigated. The X-ray diffraction (XRD) spectra indicated that the film was of polycrystalline nature. The scanning electron microscopy (SEM) images indicate that the surface morphology CdO film consists of the clusters formed with the coming together of the nanoparticles. The electrical characterization of Au/n-CdO/p–Si/Al heterojunction diode was investigated by current-voltage. The ideality factor of the diode was found to be 3.02 for room temperature. The reverse current of the diode strongly increased with illumination intensity of 100 mWcm-2 and the diode gave a maximum open circuit voltage Voc of 0.04 V and short-circuits current Isc of 9.92×10-9 A.

Keywords: CdO, heterojunction semiconductor devices, ideality factor, current-voltage characteristics

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