Search results for: dynamic power consumption

Authors: M. Yousefi, N. Nasirzadeh

Abstract:

In this paper, dynamic comparator structure employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters have been presented. The proposed comparator has low consumption thanks to power reduction methods. They have the ability for offset adjustment. The comparator consumes 14.3 μW at 100 MHz which is equal to 11.8 fJ. The comparator has been designed and simulated in 180 nm CMOS. Layouts occupy 210 μm².

Keywords: Comparator, low, power, efficiency.

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Authors: Joon-young Jung, Dong-oh Kang, Chang-seok Bae

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Power consumption is rapidly increased in data centers because the number of data center is increased and more the scale of data center become larger. Therefore, it is one of key research items to reduce power consumption in data center. The peak power of a typical server is around 250 watts. When a server is idle, it continues to use around 60% of the power consumed when in use, though vendors are putting effort into reducing this “idle" power load. Servers tend to work at only around a 5% to 20% utilization rate, partly because of response time concerns. An average of 10% of servers in their data centers was unused. In those reason, we propose dynamic power management system to reduce power consumption in green data center. Experiment result shows that about 55% power consumption is reduced at idle time.

Keywords: Data Center, Green IT, Management Server, Power Saving.

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Authors: Jörg Lenhardt, Wolfram Schiffmann, Jörg Keller

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While the feature sizes of recent Complementary Metal Oxid Semiconductor (CMOS) devices decrease the influence of static power prevails their energy consumption. Thus, power savings that benefit from Dynamic Frequency and Voltage Scaling (DVFS) are diminishing and temporal shutdown of cores or other microchip components become more worthwhile. A consequence of powering off unused parts of a chip is that the relative difference between idle and fully loaded power consumption is increased. That means, future chips and whole server systems gain more power saving potential through power-aware load balancing, whereas in former times this power saving approach had only limited effect, and thus, was not widely adopted. While powering off complete servers was used to save energy, it will be superfluous in many cases when cores can be powered down. An important advantage that comes with that is a largely reduced time to respond to increased computational demand. We include the above developments in a server power model and quantify the advantage. Our conclusion is that strategies from datacenters when to power off server systems might be used in the future on core level, while load balancing mechanisms previously used at core level might be used in the future at server level.

Keywords: Power efficiency, static power consumption, dynamic power consumption, CMOS.

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Authors: Hong Li, Linfeng Li, Jianping Hu

Abstract:

With rapid technology scaling, the proportion of the static power consumption catches up with dynamic power consumption gradually. To decrease leakage consumption is becoming more and more important in low-power design. This paper presents a power-gating scheme for P-DTGAL (p-type dual transmission gate adiabatic logic) circuits to reduce leakage power dissipations under deep submicron process. The energy dissipations of P-DTGAL circuits with power-gating scheme are investigated in different processes, frequencies and active ratios. BSIM4 model is adopted to reflect the characteristics of the leakage currents. HSPICE simulations show that the leakage loss is greatly reduced by using the P-DTGAL with power-gating techniques.

Keywords: Leakage reduction, low power, deep submicronCMOS circuits, P-type adiabatic circuits.

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Authors: M. Aleshams, A. Shahsavandi

Abstract:

This paper describes a CMOS four-quadrant multiplier intended for use in the front-end receiver by utilizing the square-law characteristic of the MOS transistor in the saturation region. The circuit is based on 0.35 um CMOS technology simulated using HSPICE software. The mixer has a third-order inter the power consumption is 271uW from a single 1.2V power supply. One of the features of the proposed design is using two MOS transistors limitation to reduce the supply voltage, which leads to reduce the power consumption. This technique provides a GHz bandwidth response and low power consumption.

Keywords: RF-Mixer, Multiplier, cut-off frequency, power consumption

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Authors: Hwan Su Jung, Ahn Jun Gil, Jong Tae Kim

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Power management techniques are necessary to save power in the microprocessor. By changing the frequency and/or operating voltage of processor, DVFS can control power consumption. In this paper, we perform a case study to find optimal power state transition for DVFS. We propose the equation to find the optimal ratio between executions of states while taking into account the deadline of processing time and the power state transition delay overhead. The experiment is performed on the Cortex-M4 processor, and average 6.5% power saving is observed when DVFS is applied under the deadline condition.

Keywords: Deadline, Dynamic Voltage Frequency Scaling, Power State Transition.

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Authors: V. Eramo, E. Miucci, A. Cianfrani, A. Germoni, M. Listanti

Abstract:

The power consumption of an Optical Packet Switch equipped with SOA technology based Spanke switching fabric is evaluated. Sophisticated analytical models are introduced to evaluate the power consumption versus the offered traffic, the main switch parameters, and the used device characteristics. The impact of Amplifier Spontaneous Emission (ASE) noise generated by a transmission system on the power consumption is investigated. As a matter of example for 32×32 switches supporting 64 wavelengths and offered traffic equal to 0,8, the average energy consumption per bit is 5, 07 · 10-2 nJ/bit and increases if ASE noise introduced by the transmission systems is increased.

Keywords: Spanke, Amplifier Spontaneous Emission Noise, Power Consumption, Optical Packet Switch.

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Authors: C. Kalamani, S. Sowmiya, S. Dheivambigai, G. Harihara Sudhan

Abstract:

Radio Frequency Identification (RFID) is a blooming technology which uses radio frequency to track the objects. This technology transmits signals between tag and reader to fetch information from the tag with a unique serial identity. Generally, the drawbacks of RFID technology are high cost, high consumption of power and weak authentication systems between a reader and a tag. The proposed protocol utilizes less dynamic power using reversible truncated multipliers which are implemented in RFID tag-reader with mutual authentication protocol system to reduce both leakage and dynamic power consumption. The proposed system was simulated using Xilinx and Cadence tools.

Keywords: Mutual authentication, protocol, reversible gates, RFID.

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Authors: Baghdasaryan Marinka

Abstract:

Monitoring the distribution of electric power consumption in the technological process of ore grinding is conducted. As a result, the impacts of the mill filling rate, the productivity of the ore supply, the volumetric density of the grinding balls, the specific density of the ground ore, and the relative speed of the mill rotation on the specific consumption of electric power have been studied. The power and technological factors affecting the reactive power generated by the synchronous motors, operating within the technological scheme are studied. A block diagram for evaluating the power consumption modes of the technological process is presented, which includes the analysis of the technological scheme, the determination of the place and volumetric density of the ore-grinding mill, the evaluation of the technological and power factors affecting the energy saving process, as well as the assessment of the electric power standards.

Keywords: Electric power standard, factor, ore grinding, power consumption, reactive power, technological.

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Authors: Pejman Hosseiniun, Rose Shayeghi, Iman Rahbari, Mohamad Reza Kalhor

Abstract:

CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell’s is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase.

Keywords: SRAM cell, CNFET, low power, HSPICE.

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Authors: Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, Ali Barati

Abstract:

This paper presents a novel CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell, and swing voltage reduced on word-lines thus dynamic power during read/write operation reduced. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load. HSPICE simulation in standard 0.25μm CMOS technology confirms all results obtained from this paper.

Keywords: Positive feedback, leakage current, read operation, write operation, dynamic energy consumption.

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Authors: Yoshifumi Sakamoto, Kouichi Ono, Takeo Nakada, Yousuke Kubo, Hiroto Yasuura

Abstract:

This paper describes a system-level SoC energy consumption estimation method based on a dynamic behavior of embedded software in the early stages of the SoC development. A major problem of SOC development is development rework caused by unreliable energy consumption estimation at the early stages. The energy consumption of an SoC used in embedded systems is strongly affected by the dynamic behavior of the software. At the early stages of SoC development, modeling with a high level of abstraction is required for both the dynamic behavior of the software, and the behavior of the SoC. We estimate the energy consumption by a UML model-based simulation. The proposed method is applied for an actual embedded system in an MFP. The energy consumption estimation of the SoC is more accurate than conventional methods and this proposed method is promising to reduce the chance of development rework in the SoC development. ∈

Keywords: SoC, Embedded Sytem, Energy Consumption, Dynamic behavior, UML, Modeling, Model-based simulation

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Authors: Dae-Hee Son, Sang-Hee Kang, Soon-Ryul Nam

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In this paper, we develop a dynamic modeling of wind farms in the Jeju power system. The dynamic model of wind farms is developed to study their dynamic effects on the Jeju power system. PSS/E is used to develop the dynamic model of a wind farm composed of 1.5-MW doubly fed induction generators. The output of a wind farm is regulated based on pitch angle control, in which the two controllable parameters are speed and power references. The simulation results confirm that the pitch angle is successfully controlled, regardless of the variation in wind speed and output regulation.

Keywords: Dynamic model, Jeju power system, pitch angle control, PSS/E, wind farm.

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Authors: M. Sedighizadeh, A. Rezazadeh

Abstract:

Based on the component approach, three kinds of dynamic load models, including a single –motor model, a two-motor model and composite load model have been developed for the stability studies of Khuzestan power system. The study results are presented in this paper. Voltage instability is a dynamic phenomenon and therefore requires dynamic representation of the power system components. Industrial loads contain a large fraction of induction machines. Several models of different complexity are available for the description investigations. This study evaluates the dynamic performances of several dynamic load models in combination with the dynamics of a load changing transformer. Case study is steel industrial substation in Khuzestan power systems.

Keywords: Dynamic load, modeling, Voltage Stability.

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Authors: Pardeep Singh, Sanjay Sharma, Parvinder S. Sandhu

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This work aims to reduce the read power consumption as well as to enhance the stability of the SRAM cell during the read operation. A new 10-transisor cell is proposed with a new read scheme to minimize the power consumption within the memory core. It has separate read and write ports, thus cell read stability is significantly improved. A 16Kb SRAM macro operating at 1V supply voltage is demonstrated in 65 nm CMOS process. Its read power consumption is reduced to 24% of the conventional design. The new cell also has lower leakage current due to its special bit-line pre-charge scheme. As a result, it is suitable for low-power mobile applications where power supply is restricted by the battery.

Keywords: A 16Kb 10T-SRAM, 4x Read-Power Reduction

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Authors: R. Manjith, C. Muthukumari

Abstract:

In this paper, a novel Linear Feedback Shift Register (LFSR) with Look Ahead Clock Gating (LACG) technique is presented to reduce the power consumption in modern processors and System-on-Chip. Clock gating is a predominant technique used to reduce unwanted switching of clock signals. Several clock gating techniques to reduce the dynamic power have been developed, of which LACG is predominant. LACG computes the clock enabling signals of each flip-flop (FF) one cycle ahead of time, based on the present cycle data of the flip-flops on which it depends. It overcomes the timing problems in the existing clock gating methods like datadriven clock gating and Auto-Gated flip-flops (AGFF) by allotting a full clock cycle for the determination of the clock enabling signals. Further to reduce the power consumption in LACG technique, FFs can be grouped so that they share a common clock enabling signal. Simulation results show that the novel grouped LFSR with LACG achieves 15.03% power savings than conventional LFSR with LACG and 44.87% than data-driven clock gating.

Keywords: AGFF, data-driven, LACG, LFSR.

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Authors: Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, Ali Barati, Ali Sarchami

Abstract:

This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during read/write operation, only selected cell connected to bit-line whereas, in conventional SRAM (CV-SRAM), all cells in selected row connected to their bit-lines, which in turn develops differential voltages across all bit-lines, and this makes energy consumption on unselected bit-lines. In proposed SRAM memory array divided into two halves and this causes data-line capacitance to reduce. Also proposed SRAM uses one bit-line and thus has lower bit-line leakage compared to CV-SRAM. Furthermore, the proposed SRAM incurs no area overhead, and has comparable read/write performance versus the CV-SRAM. Simulation results in standard 0.25μm CMOS technology shows in worst case proposed SRAM has 80% smaller dynamic energy consumption in each cycle compared to CV-SRAM. Besides, energy consumption in each cycle of proposed SRAM and CV-SRAM investigated analytically, the results of which are in good agreement with the simulation results.

Keywords: SRAM, write Operation, read Operation, capacitances, dynamic energy consumption.

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Authors: Ankit Mitra

Abstract:

An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.

Keywords: CMOS, TSPC, MTCMOS, ALU, Clock gating, power gating, pipelining.

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Authors: Tien-Shun Chan, Yung-Chung Chang, Cheng-Yu Chu, Wen-Hui Chen, Yuan-Lin Chen, Shun-Chong Wang, Chang-Chun Wang

Abstract:

98% of the energy needed in Taiwan has been imported. The prices of petroleum and electricity have been increasing. In addition, facility capacity, amount of electricity generation, amount of electricity consumption and number of Taiwan Power Company customers have continued to increase. For these reasons energy conservation has become an important topic. In the past linear regression was used to establish the power consumption models for chillers. In this study, grey prediction is used to evaluate the power consumption of a chiller so as to lower the total power consumption at peak-load (so that the relevant power providers do not need to keep on increasing their power generation capacity and facility capacity). In grey prediction, only several numerical values (at least four numerical values) are needed to establish the power consumption models for chillers. If PLR, the temperatures of supply chilled-water and return chilled-water, and the temperatures of supply cooling-water and return cooling-water are taken into consideration, quite accurate results (with the accuracy close to 99% for short-term predictions) may be obtained. Through such methods, we can predict whether the power consumption at peak-load will exceed the contract power capacity signed by the corresponding entity and Taiwan Power Company. If the power consumption at peak-load exceeds the power demand, the temperature of the supply chilled-water may be adjusted so as to reduce the PLR and hence lower the power consumption.

Keywords: Gery system theory, grey prediction, chller.

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Authors: F. Rarbi, D. Dzahini, W. Uhring

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In this paper, a dynamic and power efficient 8-bit and 100-MSPS Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is presented. The circuit uses a non-differential capacitive Digital-to-Analog (DAC) architecture segmented by 2. The prototype is produced in a commercial 65-nm 1P7M CMOS technology with 1.2-V supply voltage. The size of the core ADC is 208.6 x 103.6 µm². The post-layout noise simulation results feature a SNR of 46.9 dB at Nyquist frequency, which means an effective number of bit (ENOB) of 7.5-b. The total power consumption of this SAR ADC is only 1.55 mW at 100-MSPS. It achieves then a figure of merit of 85.6 fJ/step.

Keywords: CMOS analog to digital converter, dynamic comparator, image sensor application, successive approximation register.

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Authors: Shuen-Tai Wang, Chin-Hung Li, Ying-Chuan Chen

Abstract:

In recent years there has been renewal of interest in the relation between Green IT and Cloud Computing. The growing use of computers in cloud platform has caused marked energy consumption, putting negative pressure on electricity cost of cloud data center. This paper proposes an effective mechanism to reduce energy utilization in cloud computing environments. We present initial work on the integration of resource and power management that aims at reducing power consumption. Our mechanism relies on recalling virtualization services dynamically according to user-s virtualization request and temporarily shutting down the physical machines after finish in order to conserve energy. Given the estimated energy consumption, this proposed effort has the potential to positively impact power consumption. The results from the experiment concluded that energy indeed can be saved by powering off the idling physical machines in cloud platforms.

Keywords: Green IT, Cloud Computing, virtualization, power consumption.

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Authors: Md. Asif Jahangir Chowdhury, Md. Shahriar Rizwan, M. S. Islam

Abstract:

In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance.

Keywords: variable body biasing, state saving technique, stack effect, dual V-th, static power reduction.

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Authors: M. Honarpardaz, Z. Zhang, J. Derkx, A. Trangärd, J. Larsson

Abstract:

Pilot stages are one of the most common positioners and regulators in industry. In this paper, we present two novel concepts for pilot stages with low power consumption to regulate a pneumatic device. Pilot 1, first concept, is designed based on a conventional frame core electro-magnetic actuator and a leaf spring to control the air flow and pilot 2 has an axisymmetric actuator and spring made of non-oriented electrical steel. Concepts are simulated in a system modeling tool to study their dynamic behavior. Both concepts are prototyped and tested. Experimental results are comprehensively analyzed and compared. The most promising concept that consumes less than 8 mW is highlighted and presented.

Keywords: Electro-magnetic actuator, multidisciplinary system, low power consumption, pilot stage.

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Authors: Deogratius Musiige, François Anton, Vital Yatskevich, Laulagnet Vincent, Darka Mioc, Nguyen Pierre

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This paper presents a methodology towards the emulation of the electrical power consumption of the RF device during the cellular phone/handset transmission mode using the LTE technology. The emulation methodology takes the physical environmental variables and the logical interface between the baseband and the RF system as inputs to compute the emulated power dissipation of the RF device. The emulated power, in between the measured points corresponding to the discrete values of the logical interface parameters is computed as a polynomial interpolation using polynomial basis functions. The evaluation of polynomial and spline curve fitting models showed a respective divergence (test error) of 8% and 0.02% from the physically measured power consumption. The precisions of the instruments used for the physical measurements have been modeled as intervals. We have been able to model the power consumption of the RF device operating at 5MHz using homotopy between 2 continuous power consumptions of the RF device operating at the bandwidths 3MHz and 10MHz.

Keywords: Radio frequency, high power amplifier, baseband, LTE, power, emulation, homotopy, interval analysis, Tx power, register-transfer level.

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Authors: Darshana Thomas, Edward Wilkie, James Irvine

Abstract:

The Internet of things (IoT) is currently a highly researched topic, especially within the context of the smart home. These are small sensors that are capable of gathering data and transmitting it to a server. The majority of smart home products use protocols such as ZigBee or Bluetooth Low Energy (BLE). As these small sensors are increasing in number, the need to implement these with much more capable and ubiquitous transmission technology is necessary. The high power consumption is the reason that holds these small sensors back from using other protocols such as the most ubiquitous form of communication, WiFi. Comparing the power consumption of existing transmission technologies to one with WiFi inbuilt, would provide a better understanding for choosing between these technologies. We have developed a small IoT device with WiFi capability and proven that it is much more efficient than the first protocol, 433 MHz. We extend our work in this paper and compare WiFi power consumption with the other most widely used protocol BLE. The experimental results in this paper would conclude whether the developed prototype is capable in terms of power consumption to replace the existing protocol BLE with WiFi.

Keywords: Bluetooth, internet of things, power consumption, WiFi.

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Authors: Altab Hossain, Ataur Rahman, A. K. M. Mohiuddin, Yulfian Aminanda

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Modeling of the dynamic behavior and motion are renewed interest in the improved tractive performance of an intelligent air-cushion tracked vehicle (IACTV). This paper presents a new dynamical model for the forces on the developed small scale intelligent air-cushion tracked vehicle moving over swamp peat. The air cushion system partially supports the 25 % of vehicle total weight in order to make the vehicle ground contact pressure 7 kN/m2. As the air-cushion support system can adjust automatically on the terrain, so the vehicle can move over the terrain without any risks. The springdamper system is used with the vehicle body to control the aircushion support system on any undulating terrain by making the system sinusoidal form. Experiments have been carried out to investigate the relationships among tractive efficiency, slippage, traction coefficient, load distribution ratio, tractive effort, motion resistance and power consumption in given terrain conditions. Experiment and simulation results show that air-cushion system improves the vehicle performance by keeping traction coefficient of 71% and tractive efficiency of 62% and the developed model can meet the demand of transport efficiency with the optimal power consumption.

Keywords: Air-cushion system, ground contact pressure, slippage, power consumption.

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Authors: N. Mahendran, R. Madhuranthi

Abstract:

Wireless sensor networks (WSNs), are constantly in demand to process information more rapidly with less energy and area cost. Presently, processor based solutions have difficult to achieve high processing speed with low-power consumption. This paper presents a simple and accurate data processing scheme for low power wireless sensor node, based on reduced number of processing element (PE). The presented model provides a simple recursive structure (SRS) to process the sampled data in the wireless sensor environment and to reduce the power consumption in wireless sensor node. Based on this model, to process the incoming samples and produce a smaller amount of data sufficient to reconstruct the original signal. The ModelSim simulator used to simulate SRS structure. Functional simulation is carried out for the validation of the presented architecture. Xilinx Power Estimator (XPE) tool is used to measure the power consumption. The experimental results show the average power consumption of 91 mW; this is 42% improvement compared to the folded tree architecture.

Keywords: Power consumption, energy efficiency, low power WSN node, recursive structure, sleep/wake scheduling.

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Authors: M.Hosseinghadiry, H. Mohammadi, M.Nadisenejani

Abstract:

with increasing circuits- complexity and demand to use portable devices, power consumption is one of the most important parameters these days. Full adders are the basic block of many circuits. Therefore reducing power consumption in full adders is very important in low power circuits. One of the most powerconsuming modules in full adders is XOR/XNOR circuit. This paper presents two new full adders based on two new logic approaches. The proposed logic approaches use one XOR or XNOR gate to implement a full adder cell. Therefore, delay and power will be decreased. Using two new approaches and two XOR and XNOR gates, two new full adders have been implemented in this paper. Simulations are carried out by HSPICE in 0.18μm bulk technology with 1.8V supply voltage. The results show that the ten-transistors proposed full adder has 12% less power consumption and is 5% faster in comparison to MB12T full adder. 9T is more efficient in area and is 24% better than similar 10T full adder in term of power consumption. The main drawback of the proposed circuits is output threshold loss problem.

Keywords: Full adder, XNOR, Low power, High performance, Very Large Scale Integrated Circuit.

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Authors: Ilya Kavalchuk, Hayrettin Arisoy, Alex Stojcevski, Aman Maun Than Oo

Abstract:

Electric vehicles are one of the most complicated electric devices to simulate due to the significant number of different processes involved in electrical structure of it. There are concurrent processes of energy consumption and generation with different onboard systems, which make simulation tasks more complicated to perform. More accurate simulation on energy consumption can provide a better understanding of all energy management for electric transport. As a result of all those processes, electric transport can allow for a more sustainable future and become more convenient in relation to the distance range and recharging time. This paper discusses the problems of energy consumption simulations for electric vehicles using different software packages to provide ideas on how to make this process more precise, which can help engineers create better energy management strategies for electric vehicles.

Keywords: Electric Vehicles, EV, Power Consumption, Power Management, Simulation.

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Authors: Tatyana Aleksandrovna Barbasova, Lev Sergeevich Kazarinov, Olga Valerevna Kolesnikova, Aleksandra Aleksandrovna Filimonova

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We regard forecasting of energy consumption by private production areas of a large industrial facility as well as by the facility itself. As for production areas, the forecast is made based on empirical dependencies of the specific energy consumption and the production output. As for the facility itself, implementation of the task to minimize the energy consumption forecasting error is based on adjustment of the facility’s actual energy consumption values evaluated with the metering device and the total design energy consumption of separate production areas of the facility. The suggested procedure of optimal energy consumption was tested based on the actual data of core product output and energy consumption by a group of workshops and power plants of the large iron and steel facility. Test results show that implementation of this procedure gives the mean accuracy of energy consumption forecasting for winter 2014 of 0.11% for the group of workshops and 0.137% for the power plants.

Keywords: Energy consumption, energy consumption forecasting error, energy efficiency, forecasting accuracy, forecasting.

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