System-Level Energy Estimation for SoC based on the Dynamic Behavior of Embedded Software

Authors: Yoshifumi Sakamoto, Kouichi Ono, Takeo Nakada, Yousuke Kubo, Hiroto Yasuura

Abstract:

This paper describes a system-level SoC energy consumption estimation method based on a dynamic behavior of embedded software in the early stages of the SoC development. A major problem of SOC development is development rework caused by unreliable energy consumption estimation at the early stages. The energy consumption of an SoC used in embedded systems is strongly affected by the dynamic behavior of the software. At the early stages of SoC development, modeling with a high level of abstraction is required for both the dynamic behavior of the software, and the behavior of the SoC. We estimate the energy consumption by a UML model-based simulation. The proposed method is applied for an actual embedded system in an MFP. The energy consumption estimation of the SoC is more accurate than conventional methods and this proposed method is promising to reduce the chance of development rework in the SoC development. ∈

Keywords: SoC, Embedded Sytem, Energy Consumption, Dynamic behavior, UML, Modeling, Model-based simulation

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1327754

References:

[1] Object Management Group, http://www.omg.org/
[2] K. Ono, M. Toyota, R. Kawahara, Y. Sakamoto, T. Nakada, and N. Fukuoka, "A modeling method for performance analysis in model-driven development", Proceedings of the 13th Design, Automation and Test in Europe (DATE 2010), 2010, pp.1337-1340.
[3] K. Ono, M. Toyota, R. Kawahara, Y. Sakamoto, T. Nakada, and N. Fukuoka, "A Model-based Method for Evaluating Embedded System Performance by Abstraction of Execution Traces", Proceedings of 6th European Conference on Modeling Foundations and Applications (ECMFA 2010), Springer (2010), pp.233-244.
[4] Y. Sakamoto, T. Nagano, T. Nakada, K. Ono, K. Hisazumi, and A. Fukuda, "Development of Embedded Systems Using Reverse Engineering and Model-based Performance Evaluation", Proceedings of the 5th International Conference on Project Management (ProMAC2010), 2010, pp.160-168.
[5] J. M. Hsu and P. Banerjee. "Performance measurement and trace driven simulation of parallel CAD and numeric applications on a hypercube multicomputer". IEEE Transactions on Parallel and Distributed Systems, Vol. 3, No. 4, pp. 451.464, July 1992.
[6] C. A. Prete, G. Prina, and L. Ricciardi, "A trace-driven simulator for performance evaluation of cache-based multiprocessor systems.", IEEE Transactions on Parallel and Distributed Systems, Vol. 6, No. 9, pp. 915-929, September 1995.
[7] IEEE Std.1801, Standard for Design and Verification of Low Power Integrated Circuits, http://standards.ieee.org
[8] Y. Kanno, "Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor", Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
[9] Cadence InCyte Chip Estimator, http://www.cadence.com/products/ld/chip_estimator/pages/default.aspx
[10] A. G. Silva-Filho, R. F. Cordeiro, C. Cristiano, Ara ' ujo, A. Sarmento, M. Gomes, E. Barros, and M. E. Lima, "An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms", Hindawi Publishing Corporation, International Journal of Reconfigurable Computing, Volume 2011, Article ID 219497,
[11] N. Ohba and K. Takano, "Hardware debugging method based on signal transitions and transactions", Proceedings of the 11th Asia and South Pacific Design Automation Conference (ASP-DAC 2006), 2006, pp. 454-459.
[12] JEITA - Japan Electronics and Information Technology Industries Association, http://www.jeita.or.jp/english/
[13] IBM Rational Rhapsody, http://www-01.ibm.com/software/awdtools/rhapsody/