Search results for: successive approximation register.
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 534

Search results for: successive approximation register.

534 Implemented 5-bit 125-MS/s Successive Approximation Register ADC on FPGA

Authors: S. Heydarzadeh, A. Kadivarian, P. Torkzadeh

Abstract:

Implemented 5-bit 125-MS/s successive approximation register (SAR) analog to digital converter (ADC) on FPGA is presented in this paper.The design and modeling of a high performance SAR analog to digital converter are based on monotonic capacitor switching procedure algorithm .Spartan 3 FPGA is chosen for implementing SAR analog to digital converter algorithm. SAR VHDL program writes in Xilinx and modelsim uses for showing results.

Keywords: Analog to digital converter, Successive approximation, Capacitor switching algorithm, FPGA

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533 An 8-Bit, 100-MSPS Fully Dynamic SAR ADC for Ultra-High Speed Image Sensor

Authors: F. Rarbi, D. Dzahini, W. Uhring

Abstract:

In this paper, a dynamic and power efficient 8-bit and 100-MSPS Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is presented. The circuit uses a non-differential capacitive Digital-to-Analog (DAC) architecture segmented by 2. The prototype is produced in a commercial 65-nm 1P7M CMOS technology with 1.2-V supply voltage. The size of the core ADC is 208.6 x 103.6 µm2. The post-layout noise simulation results feature a SNR of 46.9 dB at Nyquist frequency, which means an effective number of bit (ENOB) of 7.5-b. The total power consumption of this SAR ADC is only 1.55 mW at 100-MSPS. It achieves then a figure of merit of 85.6 fJ/step.

Keywords: CMOS analog to digital converter, dynamic comparator, image sensor application, successive approximation register.

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532 High-Resolution 12-Bit Segmented Capacitor DAC in Successive Approximation ADC

Authors: Wee Leong Son, Hasmayadi Abdul Majid, Rohana Musa

Abstract:

This paper study the segmented split capacitor Digital-to-Analog Converter (DAC) implemented in a differentialtype 12-bit Successive Approximation Analog-to-Digital Converter (SA-ADC). The series capacitance split array method employed as it reduced the total area of the capacitors required for high resolution DACs. A 12-bit regular binary array structure requires 2049 unit capacitors (Cs) while the split array needs 127 unit Cs. These results in the reduction of the total capacitance and power consumption of the series split array architectures as to regular binary-weighted structures. The paper will show the 12-bit DAC series split capacitor with 4-bit thermometer coded DAC architectures as well as the simulation and measured results.

Keywords: Successive Approximation Register Analog-to- Digital Converter, SAR ADC, Low voltage ADC.

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531 Design and Implementation of a 10-bit SAR ADC

Authors: Hasmayadi Abdul Majid, Rohana Musa

Abstract:

This paper presents the development of a 38.5 kS/s 10-bit low power SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and SAR digital logic to create 10 effective bits while consuming less than 7.8 mW with a 3.3 V power supply.

Keywords: Successive Approximation Register Analog-to- Digital Converter, SAR ADC, Resistive DAC.

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530 Design and Implementation of a 10-bit SAR ADC with A Programmable Reference

Authors: Hasmayadi Abdul Majid, Yuzman Yusoff, Noor Shelida Salleh

Abstract:

This paper presents the development of a single-ended 38.5 kS/s 10-bit programmable reference SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and a SAR digital logic to create 10 effective bits ADC. A programmable reference circuitry allows the ADC to operate with different input range from 0.6 V to 2.1 V. The ADC consumed less than 7.5 mW power with a 3 V supply.

Keywords: Successive Approximation Register Analog-to- Digital Converter, SAR ADC, Resistive DAC, Programmable Reference.

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529 Design of Stable IIR Digital Filters with Specified Group Delay Errors

Authors: Yasunori Sugita, Toshinori Yoshikawa

Abstract:

The design problem of Infinite Impulse Response (IIR) digital filters is usually expressed as the minimization problem of the complex magnitude error that includes both the magnitude and phase information. However, the group delay of the filter obtained by solving such design problem may be far from the desired group delay. In this paper, we propose a design method of stable IIR digital filters with prespecified maximum group delay errors. In the proposed method, the approximation problems of the magnitude-phase and group delay are separately defined, and these two approximation problems are alternately solved using successive projections. As a result, the proposed method can design the IIR filters that satisfy the prespecified allowable errors for not only the complex magnitude but also the group delay by alternately executing the coefficient update for the magnitude-phase and the group delay approximation. The usefulness of the proposed method is verified through some examples.

Keywords: Filter design, Group delay approximation, Stable IIRfilters, Successive projection method.

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528 Best Co-approximation and Best Simultaneous Co-approximation in Fuzzy Normed Spaces

Authors: J. Kavikumar, N. S. Manian, M.B.K. Moorthy

Abstract:

The main purpose of this paper is to consider the t-best co-approximation and t-best simultaneous co-approximation in fuzzy normed spaces. We develop the theory of t-best co-approximation and t-best simultaneous co-approximation in quotient spaces. This new concept is employed us to improve various characterisations of t-co-proximinal and t-co-Chebyshev sets.

Keywords: Fuzzy best co-approximation, fuzzy quotient spaces, proximinality, Chebyshevity, best simultaneous co-approximation.

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527 Definable Subsets in Covering Approximation Spaces

Authors: Xun Ge, Zhaowen Li

Abstract:

Covering approximation spaces is a class of important generalization of approximation spaces. For a subset X of a covering approximation space (U, C), is X definable or rough? The answer of this question is uncertain, which depends on covering approximation operators endowed on (U, C). Note that there are many various covering approximation operators, which can be endowed on covering approximation spaces. This paper investigates covering approximation spaces endowed ten covering approximation operators respectively, and establishes some relations among definable subsets, inner definable subsets and outer definable subsets in covering approximation spaces, which deepens some results on definable subsets in approximation spaces.

Keywords: Covering approximation space, covering approximation operator, definable subset, inner definable subset, outer definable subset.

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526 Bias Stability of a-IGZO TFT and a new Shift-Register Design Suitable for a-IGZO TFT

Authors: Young Wook Lee, Sun-Jae Kim, Soo-Yeon Lee, Moon-Kyu Song, Woo-Geun Lee Min-Koo Han

Abstract:

We have fabricated a-IGZO TFT and investigated the stability under positive DC and AC bias stress. The threshold voltage of a-IGZO TFT shifts positively under those biases, and that reduces on-current. For this reason, conventional shift-register circuit employing TFTs which stressed by positive bias will be unstable, may do not work properly. We have designed a new 6-transistor shift-register, which has less transistors than prior circuits. The TFTs of the proposed shift-register are not suffering from positive DC or AC stress, mainly kept unbiased. Despite the compact design, the stable output signal was verified through the SPICE simulation even under RC delay of clock signal.

Keywords: Indium Gallium Zinc Oxide (IGZO), Thin FilmTransistor (TFT), shift-register

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525 A Single-Phase Register File with Complementary Pass-Transistor Adiabatic Logic

Authors: Jianping Hu, Xiaolei Sheng

Abstract:

This paper introduces an adiabatic register file based on two-phase CPAL (Complementary Pass-Transistor Adiabatic Logic circuits) with power-gating scheme, which can operate on a single-phase power clock. A 32×32 single-phase adiabatic register file with power-gating scheme has been implemented with TSMC 0.18μm CMOS technology. All the circuits except for the storage cells employ two-phase CPAL circuits, and the storage cell is based on the conventional memory one. The two-phase non-overlap power-clock generator with power-gating scheme is used to supply the proposed adiabatic register file. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. Compared with the traditional static CMOS register file, HSPICE simulations show that the proposed adiabatic register file can work very well, and it attains about 73% energy savings at 100 MHz.

Keywords: Low power, Register file, Complementarypass-transistor logic, Adiabatic logic, Single-phase power clock.

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524 On an Open Problem for Definable Subsets of Covering Approximation Spaces

Authors: Mei He, Ying Ge, Jingyu Qian

Abstract:

Let (U;D) be a Gr-covering approximation space (U; C) with covering lower approximation operator D and covering upper approximation operator D. For a subset X of U, this paper investigates the following three conditions: (1) X is a definable subset of (U;D); (2) X is an inner definable subset of (U;D); (3) X is an outer definable subset of (U;D). It is proved that if one of the above three conditions holds, then the others hold. These results give a positive answer of an open problem for definable subsets of covering approximation spaces.

Keywords: Covering approximation space, covering approximation operator, definable subset, inner definable subset, outer definable subset.

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523 Comparison between Beta Wavelets Neural Networks, RBF Neural Networks and Polynomial Approximation for 1D, 2DFunctions Approximation

Authors: Wajdi Bellil, Chokri Ben Amar, Adel M. Alimi

Abstract:

This paper proposes a comparison between wavelet neural networks (WNN), RBF neural network and polynomial approximation in term of 1-D and 2-D functions approximation. We present a novel wavelet neural network, based on Beta wavelets, for 1-D and 2-D functions approximation. Our purpose is to approximate an unknown function f: Rn - R from scattered samples (xi; y = f(xi)) i=1....n, where first, we have little a priori knowledge on the unknown function f: it lives in some infinite dimensional smooth function space and second the function approximation process is performed iteratively: each new measure on the function (xi; f(xi)) is used to compute a new estimate f as an approximation of the function f. Simulation results are demonstrated to validate the generalization ability and efficiency of the proposed Beta wavelet network.

Keywords: Beta wavelets networks, RBF neural network, training algorithms, MSE, 1-D, 2D function approximation.

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522 Some Separations in Covering Approximation Spaces

Authors: Xun Ge, Jinjin Li, Ying Ge

Abstract:

Adopting Zakowski-s upper approximation operator C and lower approximation operator C, this paper investigates granularity-wise separations in covering approximation spaces. Some characterizations of granularity-wise separations are obtained by means of Pawlak rough sets and some relations among granularitywise separations are established, which makes it possible to research covering approximation spaces by logical methods and mathematical methods in computer science. Results of this paper give further applications of Pawlak rough set theory in pattern recognition and artificial intelligence.

Keywords: Rough set, covering approximation space, granularitywise separation.

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521 An Empirical Validation of the Linear- Hyperbolic Approximation of the I-V Characteristic of a Solar Cell Generator

Authors: A. A. Penin

Abstract:

An empirical linearly-hyperbolic approximation of the I - V characteristic of a solar cell is presented. This approximation is based on hyperbolic dependence of a current of p-n junctions on voltage for large currents. Such empirical approximation is compared with the early proposed formal linearly-hyperbolic approximation of a solar cell. The expressions defining laws of change of parameters of formal approximation at change of a photo current of family of characteristics are received. It allows simplifying a finding of parameters of approximation on actual curves, to specify their values. Analytical calculation of load regime for linearly - hyperbolic model leads to quadratic equation. Also, this model allows to define soundly a deviation from the maximum power regime and to compare efficiency of regimes of solar cells with different parameters.

Keywords: a solar cell generator, I − V characteristic, p − n junction, approximation

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520 High Level Synthesis of Digital Filters Based On Sub-Token Forwarding

Authors: Iyad F. Jafar, Sandra J. Alrawashdeh, Ban K. Alhamayel

Abstract:

High level synthesis (HLS) is a process which generates register-transfer level design for digital systems from behavioral description. There are many HLS algorithms and commercial tools. However, most of these algorithms consider a behavioral description for the system when a single token is presented to the system. This approach does not exploit extra hardware efficiently, especially in the design of digital filters where common operations may exist between successive tokens. In this paper, we modify the behavioral description to process multiple tokens in parallel. However, this approach is unlike the full processing that requires full hardware replication. It exploits the presence of common operations between successive tokens. The performance of the proposed approach is better than sequential processing and approaches that of full parallel processing as the hardware resources are increased.

Keywords: Digital filters, High level synthesis, Sub-token forwarding

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519 A New Approach to Feedback Shift Registers

Authors: Myat Su Mon Win

Abstract:

The pseudorandom number generators based on linear feedback shift registers (LFSRs), are very quick, easy and secure in the implementation of hardware and software. Thus they are very popular and widely used. But LFSRs lead to fairly easy cryptanalysis due to their completely linearity properties. In this paper, we propose a stochastic generator, which is called Random Feedback Shift Register (RFSR), using stochastic transformation (Random block) with one-way and non-linearity properties.

Keywords: Linear Feedback Shift Register, Non Linearity, R_Block, Random Feedback Shift Register

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518 A Power Reduction Technique for Built-In-Self Testing Using Modified Linear Feedback Shift Register

Authors: Mayank Shakya, Soundra Pandian. K. K

Abstract:

A linear feedback shift register (LFSR) is proposed which targets to reduce the power consumption from within. It reduces the power consumption during testing of a Circuit Under Test (CUT) at two stages. At first stage, Control Logic (CL) makes the clocks of the switching units of the register inactive for a time period when output from them is going to be same as previous one and thus reducing unnecessary switching of the flip-flops. And at second stage, the LFSR reorders the test vectors by interchanging the bit with its next and closest neighbor bit. It keeps fault coverage capacity of the vectors unchanged but reduces the Total Hamming Distance (THD) so that there is reduction in power while shifting operation.

Keywords: Linear Feedback Shift Register, Total Hamming Distance, Fault Coverage, Control Logic

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517 The Performance of Alternating Top-Bottom Strategy for Successive Over Relaxation Scheme on Two Dimensional Boundary Value Problem

Authors: M. K. Hasan, Y. H. Ng, J. Sulaiman

Abstract:

This paper present the implementation of a new ordering strategy on Successive Overrelaxation scheme on two dimensional boundary value problems. The strategy involve two directions alternatingly; from top and bottom of the solution domain. The method shows to significantly reduce the iteration number to converge. Four numerical experiments were carried out to examine the performance of the new strategy.

Keywords: Two dimensional boundary value problems, Successive Overrelaxation scheme, Alternating Top-Bottom strategy, fast convergence

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516 An Approach for Vocal Register Recognition Based on Spectral Analysis of Singing

Authors: Aleksandra Zysk, Pawel Badura

Abstract:

Recognizing and controlling vocal registers during singing is a difficult task for beginner vocalist. It requires among others identifying which part of natural resonators is being used when a sound propagates through the body. Thus, an application has been designed allowing for sound recording, automatic vocal register recognition (VRR), and a graphical user interface providing real-time visualization of the signal and recognition results. Six spectral features are determined for each time frame and passed to the support vector machine classifier yielding a binary decision on the head or chest register assignment of the segment. The classification training and testing data have been recorded by ten professional female singers (soprano, aged 19-29) performing sounds for both chest and head register. The classification accuracy exceeded 93% in each of various validation schemes. Apart from a hard two-class clustering, the support vector classifier returns also information on the distance between particular feature vector and the discrimination hyperplane in a feature space. Such an information reflects the level of certainty of the vocal register classification in a fuzzy way. Thus, the designed recognition and training application is able to assess and visualize the continuous trend in singing in a user-friendly graphical mode providing an easy way to control the vocal emission.

Keywords: Classification, singing, spectral analysis, vocal emission, vocal register.

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515 Analysis of Lightweight Register Hardware Threat

Authors: Yang Luo, Beibei Wang

Abstract:

In this paper, we present a design methodology of lightweight register transfer level (RTL) hardware threat implemented based on a MAX II FPGA platform. The dynamic power consumed by the toggling of the various bit of registers as well as the dynamic power consumed per unit of logic circuits were analyzed. The hardware threat was designed taking advantage of the differences in dynamic power consumed per unit of logic circuits to hide the transfer information. The experiment result shows that the register hardware threat was successfully implemented by using different dynamic power consumed per unit of logic circuits to hide the key information of DES encryption module. It needs more than 100000 sample curves to reduce the background noise by comparing the sample space when it completely meets the time alignment requirement. In additional, an external trigger signal is playing a very important role to detect the hardware threat in this experiment.

Keywords: Side-channel analysis, hardware threat, register transfer level, dynamic power.

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514 Constant Factor Approximation Algorithm for p-Median Network Design Problem with Multiple Cable Types

Authors: Chaghoub Soraya, Zhang Xiaoyan

Abstract:

This research presents the first constant approximation algorithm to the p-median network design problem with multiple cable types. This problem was addressed with a single cable type and there is a bifactor approximation algorithm for the problem. To the best of our knowledge, the algorithm proposed in this paper is the first constant approximation algorithm for the p-median network design with multiple cable types. The addressed problem is a combination of two well studied problems which are p-median problem and network design problem. The introduced algorithm is a random sampling approximation algorithm of constant factor which is conceived by using some random sampling techniques form the literature. It is based on a redistribution Lemma from the literature and a steiner tree problem as a subproblem. This algorithm is simple, and it relies on the notions of random sampling and probability. The proposed approach gives an approximation solution with one constant ratio without violating any of the constraints, in contrast to the one proposed in the literature. This paper provides a (21 + 2)-approximation algorithm for the p-median network design problem with multiple cable types using random sampling techniques.

Keywords: Approximation algorithms, buy-at-bulk, combinatorial optimization, network design, p-median.

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513 Denoising and Compression in Wavelet Domainvia Projection on to Approximation Coefficients

Authors: Mario Mastriani

Abstract:

We describe a new filtering approach in the wavelet domain for image denoising and compression, based on the projections of details subbands coefficients (resultants of the splitting procedure, typical in wavelet domain) onto the approximation subband coefficients (much less noisy). The new algorithm is called Projection Onto Approximation Coefficients (POAC). As a result of this approach, only the approximation subband coefficients and three scalars are stored and/or transmitted to the channel. Besides, with the elimination of the details subbands coefficients, we obtain a bigger compression rate. Experimental results demonstrate that our approach compares favorably to more typical methods of denoising and compression in wavelet domain.

Keywords: Compression, denoising, projections, wavelets.

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512 Application-Specific Instruction Sets Processor with Implicit Registers to Improve Register Bandwidth

Authors: Ginhsuan Li, Chiuyun Hung, Desheng Chen, Yiwen Wang

Abstract:

Application-Specific Instruction (ASI ) set Processors (ASIP) have become an important design choice for embedded systems due to runtime flexibility, which cannot be provided by custom ASIC solutions. One major bottleneck in maximizing ASIP performance is the limitation on the data bandwidth between the General Purpose Register File (GPRF) and ASIs. This paper presents the Implicit Registers (IRs) to provide the desirable data bandwidth. An ASI Input/Output model is proposed to formulate the overheads of the additional data transfer between the GPRF and IRs, therefore, an IRs allocation algorithm is used to achieve the better performance by minimizing the number of extra data transfer instructions. The experiment results show an up to 3.33x speedup compared to the results without using IRs.

Keywords: Application-Specific Instruction-set Processors, data bandwidth, configurable processor, implicit register.

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511 A Note on Negative Hypergeometric Distribution and Its Approximation

Authors: S. B. Mansuri

Abstract:

In this paper, at first we explain about negative hypergeometric distribution and its properties. Then we use the w-function and the Stein identity to give a result on the poisson approximation to the negative hypergeometric distribution in terms of the total variation distance between the negative hypergeometric and poisson distributions and its upper bound.

Keywords: Negative hypergeometric distribution, Poisson distribution, Poisson approximation, Stein-Chen identity, w-function.

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510 The Inverse Problem of Nonsymmetric Matrices with a Submatrix Constraint and its Approximation

Authors: Yongxin Yuan, Hao Liu

Abstract:

In this paper, we first give the representation of the general solution of the following least-squares problem (LSP): Given matrices X ∈ Rn×p, B ∈ Rp×p and A0 ∈ Rr×r, find a matrix A ∈ Rn×n such that XT AX − B = min, s. t. A([1, r]) = A0, where A([1, r]) is the r×r leading principal submatrix of the matrix A. We then consider a best approximation problem: given an n × n matrix A˜ with A˜([1, r]) = A0, find Aˆ ∈ SE such that A˜ − Aˆ = minA∈SE A˜ − A, where SE is the solution set of LSP. We show that the best approximation solution Aˆ is unique and derive an explicit formula for it. Keyw

Keywords: Inverse problem, Least-squares solution, model updating, Singular value decomposition (SVD), Optimal approximation.

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509 Approximation Algorithm for the Shortest Approximate Common Superstring Problem

Authors: A.S. Rebaï, M. Elloumi

Abstract:

The Shortest Approximate Common Superstring (SACS) problem is : Given a set of strings f={w1, w2, ... , wn}, where no wi is an approximate substring of wj, i ≠ j, find a shortest string Sa, such that, every string of f is an approximate substring of Sa. When the number of the strings n>2, the SACS problem becomes NP-complete. In this paper, we present a greedy approximation SACS algorithm. Our algorithm is a 1/2-approximation for the SACS problem. It is of complexity O(n2*(l2+log(n))) in computing time, where n is the number of the strings and l is the length of a string. Our SACS algorithm is based on computation of the Length of the Approximate Longest Overlap (LALO).

Keywords: Shortest approximate common superstring, approximation algorithms, strings overlaps, complexities.

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508 Properties and Approximation Distribution Reductions in Multigranulation Rough Set Model

Authors: Properties, Approximation Distribution Reductions in Multigranulation Rough Set Model

Abstract:

Some properties of approximation sets are studied in multi-granulation optimist model in rough set theory using maximal compatible classes. The relationships between or among lower and upper approximations in single and multiple granulation are compared and discussed. Through designing Boolean functions and discernibility matrices in incomplete information systems, the lower and upper approximation sets and reduction in multi-granulation environments can be found. By using examples, the correctness of computation approach is consolidated. The related conclusions obtained are suitable for further investigating in multiple granulation RSM.

Keywords: Incomplete information system, maximal compatible class, multi-granulation rough set model, reduction.

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507 On Diffusion Approximation of Discrete Markov Dynamical Systems

Authors: Jevgenijs Carkovs

Abstract:

The paper is devoted to stochastic analysis of finite dimensional difference equation with dependent on ergodic Markov chain increments, which are proportional to small parameter ". A point-form solution of this difference equation may be represented as vertexes of a time-dependent continuous broken line given on the segment [0,1] with "-dependent scaling of intervals between vertexes. Tending " to zero one may apply stochastic averaging and diffusion approximation procedures and construct continuous approximation of the initial stochastic iterations as an ordinary or stochastic Ito differential equation. The paper proves that for sufficiently small " these equations may be successfully applied not only to approximate finite number of iterations but also for asymptotic analysis of iterations, when number of iterations tends to infinity.

Keywords: Markov dynamical system, diffusion approximation, equilibrium stochastic stability.

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506 Equalization Algorithms for MIMO System

Authors: Said Elkassimi, Said Safi, B. Manaut

Abstract:

In recent years, multi-antenna techniques are being considered as a potential solution to increase the flow of future wireless communication systems. The objective of this article is to study the emission and reception system MIMO (Multiple Input Multiple Output), and present the different reception decoding techniques. First we will present the least complex technical, linear receivers such as the zero forcing equalizer (ZF) and minimum mean squared error (MMSE). Then a nonlinear technique called ordered successive cancellation of interferences (OSIC) and the optimal detector based on the maximum likelihood criterion (ML), finally, we simulate the associated decoding algorithms for MIMO system such as ZF, MMSE, OSIC and ML, thus a comparison of performance of these algorithms in MIMO context.

Keywords: Multiple Input Multiple Outputs (MIMO), ZF, MMSE, Ordered Interference Successive Cancellation (OSIC), ML, Interference Successive Cancellation (SIC).

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505 On the Construction of m-Sequences via Primitive Polynomials with a Fast Identification Method

Authors: Abhijit Mitra

Abstract:

The paper provides an in-depth tutorial of mathematical construction of maximal length sequences (m-sequences) via primitive polynomials and how to map the same when implemented in shift registers. It is equally important to check whether a polynomial is primitive or not so as to get proper m-sequences. A fast method to identify primitive polynomials over binary fields is proposed where the complexity is considerably less in comparison with the standard procedures for the same purpose.

Keywords: Finite field, irreducible polynomial, primitive polynomial, maximal length sequence, additive shift register, multiplicative shift register.

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