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High-Efficiency Comparator for Low-Power Application
Abstract:In this paper, dynamic comparator structure employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters have been presented. The proposed comparator has low consumption thanks to power reduction methods. They have the ability for offset adjustment. The comparator consumes 14.3 μW at 100 MHz which is equal to 11.8 fJ. The comparator has been designed and simulated in 180 nm CMOS. Layouts occupy 210 μm2.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1125127Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1199
 Y. L. Wong, M. H. Cohen, & P. A. Abshire, “A 1.2-GHz comparator with adaptable offset in 0.35-m CMOS. Circuits and Systems” I: Regular Papers, IEEE Transactions on, 55(9),2008, pp. 2584-2594.
 K. Uyttenhove, & M. S. Steyaert, “Speed-power-accuracy tradeoff in high-speed CMOS ADCs”. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, 49(4), 202, pp. 280-287.
 B. Razavi, and B. A. Wooley,” Design techniques for high-speed, high-resolution comparators,” Solid-State Circuits, IEEE Journal of, 27(12), 1992, 1916-1926.
 H. Gao, P. Baltus, & Q. Meng, “Low voltage comparator for high speed ADC”. In Signals Systems and Electronics (ISSSE), International Symposium on Vol. 1, 2010, pp. 1-4.
 J. He, S. Zhan, D. Chen, & R. L. Geiger, “Analyses of static and dynamic random offset voltages in dynamic comparators,” Circuits and Systems I: Regular Papers, IEEE Transactions on, 56(5),2009, pp. 911-919.
 M. Kandala, & H. Wang, “A 0.5 V high-speed comparator with rail-to-rail input range,” Analog Integrated Circuits and Signal Processing, 73(1),2012, pp. 415-421.
 Z. Zhu, G. Yu, H. Wu, Y. Zhang, & Y. Yang, “A high-speed latched comparator with low offset voltage and low dissipation,” Analog Integrated Circuits and Signal Processing, 74(2), 2013, pp.467-471.
 T. B. Cho, & P. R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,” Solid-State Circuits, IEEE Journal of, 30(3), 1995, pp.166-172.
 V. Katyal, R. L. Geiger, & D. J. Chen, “A new high precision low offset dynamic comparator for high resolution high speed ADCs,” In Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on 2006, pp. 5-8.
 M. Hassanpourghadi, M. Zamani, & M. Sharifkhani, “A low-power low-offset dynamic comparator for analog to digital converters,” Microelectronics Journal, 45(2), 2014, pp. 256-262.
 S. Babayan-Mashhadi, & R. Lotfi, “Analysis and design of a low-voltage low-power double-tail comparator,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 22(2), 2014, pp.343-352.