Commenced in January 2007
Paper Count: 30054
High-Efficiency Comparator for Low-Power Application
Abstract:In this paper, dynamic comparator structure employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters have been presented. The proposed comparator has low consumption thanks to power reduction methods. They have the ability for offset adjustment. The comparator consumes 14.3 μW at 100 MHz which is equal to 11.8 fJ. The comparator has been designed and simulated in 180 nm CMOS. Layouts occupy 210 μm2.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1125127Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF
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