An 8-Bit, 100-MSPS Fully Dynamic SAR ADC for Ultra-High Speed Image Sensor

Authors: F. Rarbi, D. Dzahini, W. Uhring

Abstract:

In this paper, a dynamic and power efficient 8-bit and 100-MSPS Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is presented. The circuit uses a non-differential capacitive Digital-to-Analog (DAC) architecture segmented by 2. The prototype is produced in a commercial 65-nm 1P7M CMOS technology with 1.2-V supply voltage. The size of the core ADC is 208.6 x 103.6 µm². The post-layout noise simulation results feature a SNR of 46.9 dB at Nyquist frequency, which means an effective number of bit (ENOB) of 7.5-b. The total power consumption of this SAR ADC is only 1.55 mW at 100-MSPS. It achieves then a figure of merit of 85.6 fJ/step.

Keywords: CMOS analog to digital converter, dynamic comparator, image sensor application, successive approximation register.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1314841

References:

[1] Arai, T. et al., “A 252-V/lux•s, 16.7-Million-Frames-Per-Second 312-kpixel Back-Side-Illuminated Ultrahigh-Speed Charge-Coupled Device”, IEEE Transaction on Electron Devices, vol. 10, October 2013, pp. 3450-3458.
[2] Etoh, T.G et al., “A 16 Mfps 165kpixel backside-illuminated CCD,” Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International, 2011, pp.406,408.
[3] Tochigi, Y et al., A global-shutter CMOS image sensor with readout speed of 1Tpixel/s burst and 780Mpixel/s continuous, ISSCC, 2012 IEEE International, 2012, pp. 382 – 384.
[4] J. Crooks; B. Marsh; R. Turchetta; K. Taylor; W. Chan, et al. Kirana: a solid-state megapixel uCMOS image sensor for ultrahigh speed imaging, Proc. SPIE 8659, 2013, 865903, doi:10.1117/12.2011762.
[5] Bonnard, R., Guellec, F., Segura, J., Dupret, A., Uhring, W., “New 3D-integrated burst image sensor architectures with in-situ A/D conversion”, DASIP 2013, Cagliari, Italy, octobre 2013, pp 215-222.
[6] Heung Jun Jeon, Yong-Bin Kim “A CMOS low-power low-offset and high-speed fully dynamic latched comparator”, IEEE International SOC Conference, 2010, pp 285-288.
[7] William Evans, Eric Naviasky, Hao Tang, Bryan Allison, and John Matsuzaki, “Comparator Metastability Analysis”, Designers Guide.
[8] Wei., H. et al., “An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC,” IEEE J. Solid-State Circuits, vol. 47, no. 11, Nov. 2012, pp. 2763–2771.
[9] Kiyoyama, K., “A very low area adc for 3-d stacked cmos image processing system,” in 3D Systems Integration Conference (3DIC), 2011 IEEE International, Jan 2012, pp. 1–4.
[10] V. Tripathi and B. Murmann, “An 8-bit 450-MS/s single-bit/cycle SARADC in 65-nm CMOS,” in ESSCIRC (ESSCIRC), 2013 Proceedings of the, Sept 2013, pp. 117–120.