An Efficient VLSI Design Approach to Reduce Static Power using Variable Body Biasing

Authors: Md. Asif Jahangir Chowdhury, Md. Shahriar Rizwan, M. S. Islam

Abstract:

In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance.

Keywords: variable body biasing, state saving technique, stack effect, dual V-th, static power reduction.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1070615

References:

[1] S. Mutoh et al., "1-V Power Supply High-speed Digital Circuit Technology with Multithreshold-Voltage CMOS," IEEE Journal of Solis-State Circuits, Vol. 30, No. 8, pp. 847-854, August 1995.
[2] M. Powell, S.-H. Yang, B. Falsafi, K. Roy and T. N. Vijaykumar, "Gated-Vdd: A Circuit Technique to Reduce Leakage in Deepsubmicron Cache Memories," International Symposium on Low Power Electronics and Design, pp. 90-95, July 2000.
[3] J.C. Park, V. J. Mooney III and P. Pfeiffenberger, "Sleepy Stack Reduction of Leakage Power," Proceeding of the International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 148-158, September 2004.
[4] J. Park, "Sleepy Stack: a New Approach to Low Power VLSI and Memory," Ph.D. Dissertation, School of Electrical and Computer Engineering, Georgia Institute of Technology, 2005.
[Online]. Available http://etd.gatech.edu/theses
[5] J. Kao and A. Chandrakasan, "MTCMOS sequential circuits, Proc. of European Solid-State Circuits Conf., pp 332-335, September 2001.
[6] N. Karmakar, et al., "A novel dual sleep approach to low leakage and area efficient VLSI design" Proc, 2009 IEEE Regional Symposium on Micro and Nano Electronics(RSM2009), Kota Bharu, Malaysia, August 10-12, 2009, pp. 409-414.
[7] M. S. Islam, et al., “Dual Stack Method: A Novel Approach to Low Leakage and Speed Power Product VLSI Design” Proc. ICECE2010, Dhaka, Bangladesh. 18-20 December 2010, pp. 89-92
[8] www.synopsys.com
[9] http://www.eas.asu.edu/~ptm