@article{(Open Science Index):https://publications.waset.org/pdf/10008348,
	  title     = {An 8-Bit, 100-MSPS Fully Dynamic SAR ADC for Ultra-High Speed Image Sensor},
	  author    = {F. Rarbi and  D. Dzahini and  W. Uhring},
	  country	= {},
	  institution	= {},
	  abstract     = {In this paper, a dynamic and power efficient 8-bit and 100-MSPS Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is presented. The circuit uses a non-differential capacitive Digital-to-Analog (DAC) architecture segmented by 2. The prototype is produced in a commercial 65-nm 1P7M CMOS technology with 1.2-V supply voltage. The size of the core ADC is 208.6 x 103.6 µm2. The post-layout noise simulation results feature a SNR of 46.9 dB at Nyquist frequency, which means an effective number of bit (ENOB) of 7.5-b. The total power consumption of this SAR ADC is only 1.55 mW at 100-MSPS. It achieves then a figure of merit of 85.6 fJ/step.
},
	    journal   = {International Journal of Electrical and Computer Engineering},
	  volume    = {12},
	  number    = {1},
	  year      = {2018},
	  pages     = {2 - 7},
	  ee        = {https://publications.waset.org/pdf/10008348},
	  url   	= {https://publications.waset.org/vol/133},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 133, 2018},
	}