Search results for: delay analysis

Authors: Ankit Mitra

Abstract:

An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.

Keywords: CMOS, TSPC, MTCMOS, ALU, Clock gating, power gating, pipelining.

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Authors: N. Mahendran, S. Vishwaja

Abstract:

The Carry Select Adder (CSLA) is a fast adder which improves the speed of addition. From the structure of the CSLA, it is clear that there is opportunity for reducing the area. The logic operations involved in conventional CSLA and binary to excess-1 converter (BEC) based CSLA are analyzed to make a study on the data dependence and to identify redundant logic operations. In the existing adder design, the carry select (CS) operation is scheduled before the final-sum, which is different from the conventional CSLA design. In the presented scheme, Kogge stone parallel adder approach is used instead of existing adder design it will generate fast carry for intermediate stages and also improves the speed of addition. When compared to existing adder design the delay is less in the proposed adder design.

Keywords: Binary to excess-1 converter, delay, carry select adder, Kogge stone adder, speed.

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Authors: Caspar von Seckendorff, Eldar Sultanow

Abstract:

Many studies have shown that parallelization decreases efficiency [1], [2]. There are many reasons for these decrements. This paper investigates those which appear in the context of parallel data integration. Integration processes generally cannot be allocated to packages of identical size (i. e. tasks of identical complexity). The reason for this is unknown heterogeneous input data which result in variable task lengths. Process delay is defined by the slowest processing node. It leads to a detrimental effect on the total processing time. With a real world example, this study will show that while process delay does initially increase with the introduction of more nodes it ultimately decreases again after a certain point. The example will make use of the cloud computing platform Hadoop and be run inside Amazon-s EC2 compute cloud. A stochastic model will be set up which can explain this effect.

Keywords: Process delay, speedup, efficiency, parallel computing, data integration, E-Commerce, Amazon Elastic Compute Cloud (EC2), Hadoop, Nutch.

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Authors: Sun-Young Jang, Sung-Ah Kim, Dongyoun Shin

Abstract:

The Intelligent transportation system is essential to build smarter cities. Machine learning based transportation prediction could be highly promising approach by delivering invisible aspect visible. In this context, this research aims to make a prototype model that predicts transportation network by using big data and machine learning technology. In detail, among urban transportation systems this research chooses bus system.  The research problem that existing headway model cannot response dynamic transportation conditions. Thus, bus delay problem is often occurred. To overcome this problem, a prediction model is presented to fine patterns of bus delay by using a machine learning implementing the following data sets; traffics, weathers, and bus statues. This research presents a flexible headway model to predict bus delay and analyze the result. The prototyping model is composed by real-time data of buses. The data are gathered through public data portals and real time Application Program Interface (API) by the government. These data are fundamental resources to organize interval pattern models of bus operations as traffic environment factors (road speeds, station conditions, weathers, and bus information of operating in real-time). The prototyping model is designed by the machine learning tool (RapidMiner Studio) and conducted tests for bus delays prediction. This research presents experiments to increase prediction accuracy for bus headway by analyzing the urban big data. The big data analysis is important to predict the future and to find correlations by processing huge amount of data. Therefore, based on the analysis method, this research represents an effective use of the machine learning and urban big data to understand urban dynamics.

Keywords: Big data, bus headway prediction, machine learning, public transportation.

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Authors: Venkatesh C., K. Shanti Swarup

Abstract:

This paper investigates the impact on operating time delay and relay maloperation when 1st,2nd and 3rd order analog antialiasing filters are used in numerical distance protection. RC filter with cut-off frequency 90 Hz is used. Simulations are carried out for different SIR (Source to line Impedance Ratio), load, fault type and fault conditions using SIMULINK, where the voltage and current signals are fed online to the developed numerical distance relay model. Matlab is used for plotting the impedance trajectory. Investigation results shows that, about 75 % of the simulated cases, numerical distance relay operating time is not increased even-though there is a time delay when higher order filters are used. Relay maloperation (selectivity) also reduces (increases) when higher order filters are used in numerical distance protection.

Keywords: Antialiasing, capacitive voltage transformers, delay estimation, discrete Fourier transform (DFT), distance measurement, low-pass filters, source to line impedance ratio (SIR), protective relaying.

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Authors: Farzana Yasmeen, Md. Nurul Huda, Md. Enamul Haque, Michihiro Aoki, Shigeki Yamada

Abstract:

Delay-Tolerant Networks (DTNs) are sparse, wireless networks where disconnections are common due to host mobility and low node density. The Message Ferrying (MF) scheme is a mobilityassisted paradigm to improve connectivity in DTN-like networks. A ferry or message ferry is a special node in the network which has a per-determined route in the deployed area and relays messages between mobile hosts (MHs) which are intermittently connected. Increased contact opportunities among mobile hosts and the ferry improve the performance of the network, both in terms of message delivery ratio and average end-end delay. However, due to the inherent mobility of mobile hosts and pre-determined periodicity of the message ferry, mobile hosts may often -miss- contact opportunities with a ferry. In this paper, we propose the combination of stationary ferry access points (FAPs) with MF routing to increase contact opportunities between mobile hosts and the MF and consequently improve the performance of the DTN. We also propose several placement models for deploying FAPs on MF routes. We evaluate the performance of the FAP placement models through comprehensive simulation. Our findings show that FAPs do improve the performance of MF-assisted DTNs and symmetric placement of FAPs outperforms other placement strategies.

Keywords: Service infrastructure, delay-tolerant network, messageferry routing, placement models.

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Authors: T.Sheela, Dr.J.Raja

Abstract:

Continuously growing needs for Internet applications that transmit massive amount of data have led to the emergence of high speed network. Data transfer must take place without any congestion and hence feedback parameters must be transferred from the receiver end to the sender end so as to restrict the sending rate in order to avoid congestion. Even though TCP tries to avoid congestion by restricting the sending rate and window size, it never announces the sender about the capacity of the data to be sent and also it reduces the window size by half at the time of congestion therefore resulting in the decrease of throughput, low utilization of the bandwidth and maximum delay. In this paper, XCP protocol is used and feedback parameters are calculated based on arrival rate, service rate, traffic rate and queue size and hence the receiver informs the sender about the throughput, capacity of the data to be sent and window size adjustment, resulting in no drastic decrease in window size, better increase in sending rate because of which there is a continuous flow of data without congestion. Therefore as a result of this, there is a maximum increase in throughput, high utilization of the bandwidth and minimum delay. The result of the proposed work is presented as a graph based on throughput, delay and window size. Thus in this paper, XCP protocol is well illustrated and the various parameters are thoroughly analyzed and adequately presented.

Keywords: Bandwidth-Delay Product, Congestion Control, Congestion Window, TCP/IP

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Authors: P.Ramanathan, P.T.Vanathi

Abstract:

Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and the growing needs of portable devices, low-power and highperformance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, fan-out and interconnect count of logic circuits. In this paper, a new architecture for performing 8-bit, 16-bit and 32-bit Parallel Prefix addition is proposed. The proposed prefix adder structures is compared with several classical adders of same bit width in terms of power, delay and number of computational nodes. The results reveal that the proposed structures have the least power delay product when compared with its peer existing Prefix adder structures. Tanner EDA tool was used for simulating the adder designs in the TSMC 180 nm and TSMC 130 nm technologies.

Keywords: Parallel Prefix Adder (PPA), Dot operator, Semi-Dotoperator, Complementary Metal Oxide Semiconductor (CMOS), Odd-dot operator, Even-dot operator, Odd-semi-dot operator andEven-semi-dot operator.

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Authors: Guo-Ming Sung, Naga Raju Naik R.

Abstract:

Paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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Authors: P.S. Prakash, S. Selvan

Abstract:

IP networks are evolving from data communication infrastructure into many real-time applications such as video conferencing, IP telephony and require stringent Quality of Service (QoS) requirements. A rudimentary issue in QoS routing is to find a path between a source-destination pair that satisfies two or more endto- end constraints and termed to be NP hard or complete. In this context, we present an algorithm Multi Constraint Path Problem Version 3 (MCPv3), where all constraints are approximated and return a feasible path in much quicker time. We present another algorithm namely Delay Coerced Multi Constrained Routing (DCMCR) where coerce one constraint and approximate the remaining constraints. Our algorithm returns a feasible path, if exists, in polynomial time between a source-destination pair whose first weight satisfied by the first constraint and every other weight is bounded by remaining constraints by a predefined approximation factor (a). We present our experimental results with different topologies and network conditions.

Keywords: Routing, Quality-of-Service (QoS), additive constraints, shortest path, delay coercion.

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Authors: Seongmin Yim

Abstract:

The Korean government has applied preliminary feasibility study for new and huge R&D programs since 2008.The study is carried out from the viewpoints of technology, policy, and Economics. Then integrate the separate analysis and finally arrive at a definite result; whether a program is feasible or unfeasible, This paper describes the concept and method of the feasibility analysis focused on technological viability assessment for technical analysis. It consists of technology trend assessment and technology level assessment. Through the analysis, we can determine the chance of schedule delay or cost overrun occurring in the proposed plan.

Keywords: Preliminary Feasibility Study, Technological viability, Technology Trend Assessment, Technology Level Assessment

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Authors: Pham Luu Trung Duong, Moonyong Lee

Abstract:

To increase precision and reliability of automatic control systems, we have to take into account of random factors affecting the control system. Thus, operational matrix technique is used for statistical analysis of first order plus time delay system with uniform random parameter. Examples with deterministic and stochastic disturbance are considered to demonstrate the validity of the method. Comparison with Monte Carlo method is made to show the computational effectiveness of the method.

Keywords: First order plus dead-time, Operational matrix, Statistical analysis, Walsh function.

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Authors: Nemat Abazari, Reza Abazari

Abstract:

In this work, we successfully extended one-dimensional differential transform method (DTM), by presenting and proving some theorems, to solving nonlinear high-order multi-pantograph equations. This technique provides a sequence of functions which converges to the exact solution of the problem. Some examples are given to demonstrate the validity and applicability of the present method and a comparison is made with existing results.

Keywords: Nonlinear multi-pantograph equation, delay differential equation, differential transformation method, proportional delay conditions, closed form solution.

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Authors: Ahmed Madian, Muaz Aljarhi

Abstract:

Coordinate Rotation Digital Computer (CORDIC) is a unique digital computing unit intended for the computation of mathematical operations and functions. This paper presents A multi CORDIC processor that integrates different CORDIC architectures on a single FPGA chip and allows the user to select the CORDIC architecture to proceed with based on what he wants to calculate and his needs. Synthesis show that radix 2 CORDIC has the lowest clock delay, radix 8 CORDIC has the highest LUT usage and lowest register usage while Hybrid Radix 4 CORDIC had the highest clock delay.

Keywords: Multi, CORDIC, FPGA, Processor.

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Authors: Roengruen P., Tipsuwanporn V., Puawade P., Numsomran A.

Abstract:

Smith Predictor control is theoretically a good solution to the problem of controlling the time delay systems. However, it seldom gets use because it is almost impossible to find out a precise mathematical model of the practical system and very sensitive to uncertain system with variable time-delay. In this paper is concerned with a design method of smith predictor for temperature control system by Coefficient Diagram Method (CDM). The simulation results show that the control system with smith predictor design by CDM is stable and robust whilst giving the desired time domain system performance.

Keywords: CDM, Smith Predictor, temperature process

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Authors: Changchun Shen, Shouming Zhong

Abstract:

This paper investigates the robust stability of uncertain neutral system with time-varying delay. By using Lyapunov method and linear matrix inequality technology, new delay-dependent stability criteria are obtained and formulated in terms of linear matrix inequalities (LMIs), which can be easy to check the robust stability of the considered systems. Numerical examples are given to indicate significant improvements over some existing results.

Keywords: Neutral system, linear matrix inequalities, Lyapunov, stability.

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Authors: Da-Xue Chen, Guang-Hui Liu

Abstract:

In this paper, we study the oscillation of a class of second-order nonlinear neutral damped variable delay dynamic equations on time scales. By using a generalized Riccati transformation technique, we obtain some sufficient conditions for the oscillation of the equations. The results of this paper improve and extend some known results. We also illustrate our main results with some examples.

Keywords: Oscillation theorem, second-order nonlinear neutral dynamic equation, variable delay, damping, Riccati transformation.

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Authors: Mehdi Alilou, Mehdi Dehghan

Abstract:

Routing in mobile ad hoc networks is a challenging task because nodes are free to move randomly. In DSR like all On- Demand routing algorithms, route discovery mechanism is associated with great delay. More Clearly in DSR routing protocol to send route reply packet, when current route breaks, destination seeks a new route. In this paper we try to change route selection mechanism proactively. We also define a link stability parameter in which a stability value is assigned to each link. Given this feature, destination node can estimate stability of routes and can select the best and more stable route. Therefore we can reduce the delay and jitter of sending data packets.

Keywords: DSR, MANET, proactive, routing.

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Authors: M. M. Seraj, M. S. Gadala

Abstract:

This study presents a systematic analysis of wetted region due to cooling of aluminum plate by water spray impingement with respect to different water flow rates, spray nozzle heights, and subcooling. Unlike jet impingement, the wetting is not commenced upon spray impingement and there is a delay in wetness of hot test surface. After initiation, the wetting (black zone) progresses gradually to cover all test plate and provides efficient cooling in nucleate boiling regime. Generally, spray cooling is found function of spray flow rate, spray-to-surface distance and water subcooling. Wetting delay is decreasing by increasing of spray flow rate until spray impact area is not become bigger that test surface. Otherwise, higher spray flow rate is not practically accelerated start of wetting. Very fast wetting due to spray cooling can be obtained by dense spray (high floe rate) discharged from adjacent nozzle to the test surface. Highly subcooling water spray also triggers earlier wetting of hot aluminum plate.

Keywords: Water spray, wetting, aluminum plate, flow rate.

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Authors: Kejun Zhuang

Abstract:

In this paper, a delayed physiological control system is investigated. The sufficient conditions for stability of positive equilibrium and existence of local Hopf bifurcation are derived. Furthermore, global existence of periodic solutions is established by using the global Hopf bifurcation theory. Finally, numerical examples are given to support the theoretical analysis.

Keywords: Physiological control system, global Hopf bifurcation, periodic solutions.

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Authors: Sorore Benabid

Abstract:

The Q-enhanced LC filters are the most used architecture in the Bandpass (BP) Continuous-Time (CT) Delta-Sigma (ΣΔ) modulators, due to their: high frequencies operation, high linearity than the active filters and a high quality factor obtained by Q-enhanced technique. This technique consists of the use of a negative resistance that compensate the ohmic losses in the on-chip inductor. However, this technique introduces a zero in the filter transfer function which will affect the modulator performances in term of Dynamic Range (DR), stability and in-band noise (Signal-to-Noise Ratio (SNR)). In this paper, we study the effect of this zero and we demonstrate that a calibration of the excess loop delay (ELD) is required to ensure the best performances of the modulator. System level simulations are done for a 2ndorder BP CT (ΣΔ) modulator at a center frequency of 300MHz. Simulation results indicate that the optimal ELD should be reduced by 13% to achieve the maximum SNR and DR compared to the ideal LC-based ΣΔ modulator.

Keywords: Continuous-time bandpass delta-sigma modulators, excess loop delay, on-chip inductor, Q-enhanced LC filter.

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Authors: Shobha Sharma, Amita Dev

Abstract:

Data driven dynamic logic is the high speed dynamic circuit with low area. The clock of the dynamic circuit is removed and data drives the circuit instead of clock for precharging purpose. This data driven dynamic nand gate is given static forward substrate biasing of Vsupply/2 as well as the substrate bias is connected to the input data, resulting in dynamic substrate bias. The dynamic substrate bias gives the shortest propagation delay with a penalty on the power dissipation. Propagation delay is reduced by 77.8% compared to the normal reverse substrate bias Data driven dynamic nand. Also dynamic substrate biased D3nand’s propagation delay is reduced by 31.26% compared to data driven dynamic nand gate with static forward substrate biasing of Vdd/2. This data driven dynamic nand gate with dynamic body biasing gives us the highest speed with no area penalty and finds its applications where power penalty is acceptable. Also combination of Dynamic and static Forward body bias can be used with reduced propagation delay compared to static forward biased circuit and with comparable increase in an average power. The simulations were done on hspice simulator with 22nm High-k metal gate strained Si technology HP models of Arizona State University, USA.

Keywords: Data driven nand gate, dynamic substrate biasing, nand gate, static substrate biasing.

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Authors: Zixin Liu, Shu Lü, Shouming Zhong, Mao Ye

Abstract:

In this paper, the robust exponential stability problem of uncertain discrete-time recurrent neural networks with timevarying delay is investigated. By constructing a new augmented Lyapunov-Krasovskii function, some new improved stability criteria are obtained in forms of linear matrix inequality (LMI). Compared with some recent results in literature, the conservatism of the new criteria is reduced notably. Two numerical examples are provided to demonstrate the less conservatism and effectiveness of the proposed results.

Keywords: Robust exponential stability, delay-dependent stability, discrete-time neutral networks, time-varying delays.

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Authors: Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj

Abstract:

Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.

Keywords: Deep submicron, Leakage Current, LECTOR, ONOFIC, Power Delay Product

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Authors: Hsin-Yun Lee

Abstract:

In this study, the pedestrian simulation VISWALK integration and application platform ant algorithms written program made to construct a renovation engineering schedule planning mode. The use of simulation analysis platform construction site when the user running the simulation, after calculating the user walks in the case of construction delays, the ant algorithm to find out the minimum delay time schedule plan, and add volume and unit area deactivated loss of business computing, and finally to the owners and users of two different positions cut considerations pick out the best schedule planning. To assess and validate its effectiveness, this study constructed the model imported floor of a shopping mall floor renovation engineering cases. Verify that the case can be found from the mode of the proposed project schedule planning program can effectively reduce the delay time and the user's walking mall loss of business, the impact of the operation on the renovation engineering facilities in the building to a minimum.

Keywords: Pedestrian, renovation, schedule, simulation.

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Authors: K. Navaz, Kannan Balasubramanian

Abstract:

Due to the increasing growth of internet users, the emerging applications of multicast are growing day by day and there is a requisite for the design of high-speed switches/routers. Huge amounts of effort have been done into the research area of multicast switch fabric design and algorithms. Different traffic scenarios are the influencing factor which affect the throughput and delay of the switch. The pointer based multicast scheduling algorithms are not performed well under non-uniform traffic conditions. In this work, performance of the switch has been analyzed by applying the advanced multicast scheduling algorithm OQSMS (Optimal Queue Selection Based Multicast Scheduling Algorithm), MDDR (Multicast Due Date Round-Robin Scheduling Algorithm) and MDRR (Multicast Dual Round-Robin Scheduling Algorithm). The results show that OQSMS achieves better switching performance than other algorithms under the uniform, non-uniform and bursty traffic conditions and it estimates optimal queue in each time slot so that it achieves maximum possible throughput.

Keywords: Multicast, Switch, Delay, Scheduling.

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Authors: R. Hanuma Naik, D. V. Ashok Kumar, K. S. R. Anjaneyulu

Abstract:

Several of the practical industrial control processes are multivariable processes. Due to the relation amid the variables (interaction), delay in the loops, it is very intricate to design a controller directly for these processes. So first, the interaction of the variables is analyzed using Relative Normalized Gain Array (RNGA), which considers the time constant, static gain and delay time of the processes. Based on the effect of RNGA, relative gain array (RGA) and NI, the pair (control configuration) of variables to be controlled by decentralized control is selected. The equivalent transfer function (ETF) of the process model is estimated as first order process with delay using the corresponding elements in the Relative gain array and Relative average residence time array (RARTA) of the processes. Secondly, a decentralized Proportional- Integral (PI) controller is designed for each ETF simply using frequency response specifications. Finally, the performance and robustness of the algorithm is comparing with existing related approaches to validate the effectiveness of the projected algorithm.

Keywords: Decentralized control, interaction, Multivariable processes, relative normalized gain array, relative average residence time array, steady state gain.

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Authors: Se-Jin Ko, Deok-Min Kim, Seok-Yoon Kim

Abstract:

The trend of growing density on chips has increases not only the temperature in chips but also the gradient of the temperature depending on locations. In this paper, we propose the balanced skew tree generation technique for minimizing the clock skew that is affected by the temperature gradients on chips. We calculate the interconnect delay using Elmore delay equation, and find out the optimal balanced clock tree by modifying the clock trees generated through the Deferred Merge Embedding(DME) algorithm. The experimental results show that the distance variance of clock insertion points with and without considering the temperature gradient can be lowered below 54% and we confirm that the skew is remarkably decreased after applying the proposed technique.

Keywords: clock, clock-skew, temperature, thermal.

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Authors: Zixin Liu

Abstract:

The problem of robust stability and robust stabilization for a class of discrete-time uncertain systems with time delay is investigated. Based on Tchebychev inequality, by constructing a new augmented Lyapunov function, some improved sufficient conditions ensuring exponential stability and stabilization are established. These conditions are expressed in the forms of linear matrix inequalities (LMIs), whose feasibility can be easily checked by using Matlab LMI Toolbox. Compared with some previous results derived in the literature, the new obtained criteria have less conservatism. Two numerical examples are provided to demonstrate the improvement and effectiveness of the proposed method.

Keywords: Robust stabilization, robust stability, discrete-time system, time delay.

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Authors: Qingqing Wang, Shouming Zhong

Abstract:

This paper is concerned with the stability problem with two additive time-varying delay components. By choosing one augmented Lyapunov-Krasovskii functional, using some new zero equalities, and combining linear matrix inequalities (LMI) techniques, two new sufficient criteria ensuring the global stability asymptotic stability of DNNs is obtained. These stability criteria are present in terms of linear matrix inequalities and can be easily checked. Finally, some examples are showed to demonstrate the effectiveness and less conservatism of the proposed method.

Keywords: Neural networks, Globally asymptotic stability, LMI approach, Additive time-varying delays.

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