Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 30127
The Excess Loop Delay Calibration in a Bandpass Continuous-Time Delta Sigma Modulators Based on Q-Enhanced LC Filter

Authors: Sorore Benabid

Abstract:

The Q-enhanced LC filters are the most used architecture in the Bandpass (BP) Continuous-Time (CT) Delta-Sigma (ΣΔ) modulators, due to their: high frequencies operation, high linearity than the active filters and a high quality factor obtained by Q-enhanced technique. This technique consists of the use of a negative resistance that compensate the ohmic losses in the on-chip inductor. However, this technique introduces a zero in the filter transfer function which will affect the modulator performances in term of Dynamic Range (DR), stability and in-band noise (Signal-to-Noise Ratio (SNR)). In this paper, we study the effect of this zero and we demonstrate that a calibration of the excess loop delay (ELD) is required to ensure the best performances of the modulator. System level simulations are done for a 2ndorder BP CT (ΣΔ) modulator at a center frequency of 300MHz. Simulation results indicate that the optimal ELD should be reduced by 13% to achieve the maximum SNR and DR compared to the ideal LC-based ΣΔ modulator.

Keywords: Continuous-time bandpass delta-sigma modulators, excess loop delay, on-chip inductor, Q-enhanced LC filter.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1315605

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 339

References:


[1] S. Gupta, D. Gangopadhyay, H. Lakdawala, J. C. Rudell, and D. J. Allstot, “A 0.8-2 GHz fully-integrated QPLL-timed direct-RF-sampling bandpass ΣΔ ADC in 0.13 μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 47, no. 5, pp. 1141–1153, May 2012.
[2] G. Molina-Salgado, A. Morgado, G. J. Dolecek, and J. M. de la Rosa, “LC-based bandpass continuous-time sigma-delta modulators with widely tunable notch frequency,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 5, pp. 1442–1455, May 2014.
[3] J. Lota and A. Demosthenous, “Q-enhancement with on-chip inductor optimization for reconfigurable ΔΣ radio-frequency ADC,” in 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), June 2015, pp. 1–4.
[4] G. M. Salgado, G. J. Dolecek, and J. M. de la Rosa, “On the use of passive circuits to implement LC-based band-pass CT ΣΔ modulators,” in 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), Aug 2015, pp. 1–4.
[5] J. A. Cherry and W. M. Snelgrove, “Excess loop delay in continuous-time delta-sigma modulators,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 4, pp. 376–389, Apr 1999.
[6] S. Loeda, H. M. Reekie, and B. Mulgrew, “On the design of high-performance wide-band continuous-time sigma-delta converters using numerical optimization,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, no. 4, pp. 802–810, April 2006.
[7] C.-Y. Cai, Y. Jiang, S.-W. Sin, S.-P. U, and R. P. Martins, “Excess-loop-delay compensation technique for CT ΣΔ modulator with hybrid active–passive loop-filters,” Analog Integrated Circuits and Signal Processing, vol. 76, no. 1, pp. 35–46, Jul 2013. (Online). Available: https://doi.org/10.1007/s10470-013-0069-z
[8] A. Yahia, P. Benabes, and R. Kielbasa, “The influence of the feedback DAC delay in continuous-time bandpass DS converters,” May 2001, pp. 716–719.
[9] A. Ashry and H. Aboushady, “Using excess loop delay to simplify LC-based ΣΔ modulators,” Electronics Letters, vol. 45, no. 25, pp. 1298–1299, December 2009.