Performance Analysis of High Speed Adder for DSP Applications
The Carry Select Adder (CSLA) is a fast adder which improves the speed of addition. From the structure of the CSLA, it is clear that there is opportunity for reducing the area. The logic operations involved in conventional CSLA and binary to excess-1 converter (BEC) based CSLA are analyzed to make a study on the data dependence and to identify redundant logic operations. In the existing adder design, the carry select (CS) operation is scheduled before the final-sum, which is different from the conventional CSLA design. In the presented scheme, Kogge stone parallel adder approach is used instead of existing adder design it will generate fast carry for intermediate stages and also improves the speed of addition. When compared to existing adder design the delay is less in the proposed adder design.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1127172Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 993
 Allipeera, K. and Ahmed Basha, S. “An Efficient 64-Bit Carry Select Adder with Less Delay and Reduced Area Application”, International Journal of Engineering Research and Applications (IJERA), 2012, vol.2, pp.78-84.
 Ramkumar and Kittur, H.M., “Low-power and area-efficient carry-select adder”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.20, 2012, pp.371–375.
 Kim, Y. and Kim, L., “64-bit carry-select adder with reduced area”, Electron. Lett, 2001, vol. 10, pp.614–615.
 He, Y. and Chang, C.H., “An area efficient 64-bit square root carry select adder for low power application”, in Proc. IEEE Int. Symp. Circuits Syst, 2005, vol.4, pp.4082–4085.
 Wey, I. and Ho, C., “An area-efficient carry select adder design by sharing the common Boolean logic term”, in Proc. IMECS, vol.10,2012, pp.1-4.
 Manju, S. and Sornagopal, V., “An efficient SQRT architecture of carry select adder design by common Boolean logic”, in Proc. VLSI ICEVENT, vol.16, 2013, pp.1-5.
 Chaitanya kumara, P. and Nagendra, R., “Design of 32 bit Parallel Prefix Adders”, IOSR Journal of Electronics and Communication Engineering (IOSR-JECE), vol.15, 2013, pp.150-160.
 Partha Mitra and Debarshi Datta, “Low Power High Speed SQRT Carry Select Adder”, IOSR Journal of VLSI and Signal Processing,2013, vol.1, pp.46-51.
 Sarabdeep Singh and Dilip Kumar, “Design of area and power efficient modified carry select adder”, International journal of computer application, 2011, vol.33.
 Ch. Pavan kumar and V. Narayana Reddy, “Design and Implementation of Modified Sqrt Carry Select Adder on FPGA”, International Journal of Computer Trends and Technology (IJCTT), 2013, vol.5, pp.63-68.
 Pandu Ranga Rao and Priyanka Halle, “An Efficient Carry Select Adder with Less Delay and Reduced Area Application”, IJETT, vol.4,2013, pp.3766-3770.
 Dr. P. Bhaskara Reddy, S.V.S. Prasad, K. Ananda Kumar, “An Area and Speed Efficient Square Root Carry Select Adder Using Optimized Logic Units”, International Journal of Innovative Research in Computer Science & Technology (IJIRCST), Volume-3, Issue-5, 2015.
 Pandu Ranga Rao & Priyanka Halle, An Efficient Carry Select Adder with Less Delay and Reduced Area Application, IJETT, volume 4, issue 9,2013.
 Gauravkumar D. Jade, Asst. Prof. Prafful Dubey, Prof. Vijay Sharma, “Delay & Area Efficient Carry-Select Adder”, IORD Journal of Science & Technology, Volume 2, Issue 2, 2015, pp. 47-52.
 Basant Kumar Mohanty & Sujit Kumar Patel, Area–Delay–Power Efficient Carry-Select Adder, IEEE transactions on circuits and systems II: express briefs, vol.61, no.6, 2014.
 Pakkiraiah Chakali, Madhu Kumar Patnala, “Design of High Speed Kogge-Stone Based Carry Select Adder”, International Journal of Emerging Science and Engineering (IJESE), Volume-1, Issue-4, 2013.
 Mohammed Haseena Begum and Vamsi Mohana Krishna, V., “Design and Verification of Low Power and Area Effcient Kogge-Stone Carry Select Adder”, International Journal of Engineering Research & Technology (IJERT), vol.8, 2013, pp.463-467.
 Gagandeep Singh and Chakshu Goel, “Area Efficient Carry Select Adder (AE-CSLA) using Cadence Tools”, International Journal of Engineering Trends and Technology (IJETT), vol.10, 2013, pp.23-26.
 Deepthi Obul Reddy and Ramesh Yadav, P., “Carry Select Adder with Low Power and Area Efficiency”, IJERD,2012, vol.3, pp.29-35.
 Shuchi Verma and Sampath Kumar, “Design & Analysis of Low Power, Area-Efficient Carry Select Adder”, Int. Journal of Engineering Research and Applications, 2012, vol.4, pp.53-55.