Search results for: single-path delay feedback

Authors: Yanling Zhu, Kai Wang

Abstract:

By means of Mawhin’s continuation theorem, we study a kind of third-order p-Laplacian functional differential equation with distributed delay in the form: ϕp(x (t)) = g  t,  0 −τ x(t + s) dα(s)  + e(t), some criteria to guarantee the existence of periodic solutions are obtained.

Keywords: p–Laplacian, distributed delay, periodic solution, Mawhin's continuation theorem.

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Authors: Jirawat Thaenthong, Steven Gordon

Abstract:

MANEMO is the integration of Network Mobility (NEMO) and Mobile Ad Hoc Network (MANET). A MANEMO node has an interface to both a MANET and NEMO network, and therefore should choose the optimal interface for packet delivery, however such a handover between interfaces will introduce packet loss. We define the steps necessary for a MANEMO handover, using Mobile IP and NEMO to signal the new binding to the relevant Home Agent(s). The handover steps aim to minimize the packet loss by avoiding waiting for Duplicate Address Detection and Neighbour Unreachability Detection. We present expressions for handover delay and packet loss, and then use numerical examples to evaluate a MANEMO handover. The analysis shows how the packet loss depends on level of nesting within NEMO, the delay between Home Agents and the load on the MANET, and hence can be used to developing optimal MANEMO handover algorithms.

Keywords: IP mobility, handover, MANET, network mobility

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Authors: Yong Li

Abstract:

The paper is concerned with the existence of solution of nonlinear second order neutral stochastic differential inclusions with infinite delay in a Hilbert Space. Sufficient conditions for the existence are obtained by using a fixed point theorem for condensing maps.

Keywords: Mild solution, Convex multivalued map, Neutral stochastic differential inclusions.

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Authors: G.Ramana Murthy, C.Senthilpari, P.Velrajkumar, Lim Tien Sze

Abstract:

The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other existing six adder circuits in terms of power, propagation delay and PDP. The proposed adder circuit is further analyzed for interconnect analysis, which gives better performance than other adder circuits in terms of layout thickness, width and height.

Keywords: Full Adder, Interconnect Analysis, Low-Power, Multiplexer, Propagation Delay, Parametric Analysis.

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Authors: Ali Kartal

Abstract:

According to the new developments in the field of information and communication technologies, the necessity arises for active use of these new technologies in education. It is clear that the integration of technology in education system will be different for primary-higher education or traditional- distance education. In this study, the subject of the integration of technology for distance education was discussed. The subject was taken from the viewpoint of students. With using the information of student feedback about education program in which new technological medias are used, how can survey variables can be separated into the factors as positive, negative and supporter and how can be redesigned education strategy of the higher education associations with the examining the variables of each determinated factor is explained. The paper concludes with the recommendations about the necessitity of working as a group of different area experts and using of numerical methods in establishing of education strategy to be successful.

Keywords: Distance education, student feedback, working as a group, numerical methods.

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Authors: D. Muley, H. S. Al-Mandhari

Abstract:

This paper evaluates the performance of a multi-lane four legged modern roundabout operating in Muscat using SIDRA model. The performance measures include Degree of Saturation (DOS), average delay, and queue lengths. The geometric and traffic data were used for model preparation. Gap acceptance parameters, critical gap and follow up headway, were used for calibration of SIDRA model. The results from the analysis showed that currently the roundabout is experiencing delays up to 610 seconds per vehicle with DOS 1.67 during peak hour. Further, sensitivity analysis for general and roundabout parameters was performed, amongst lane width, cruise speed, inscribed diameter, entry radius and entry angle showed that inscribed diameter is most crucial factor affecting delay and DOS. Up gradation of roundabout to fully signalized junction was found as the suitable solution which will serve for future years with LOS C for design year having DOS of 0.9 with average control delay of 51.9 seconds per vehicle.

Keywords: Performance analysis, roundabout, sensitivity analysis, SIDRA.

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Authors: S. Balaji, M. Rajaram, Y. Harold Robinson, E. Golden Julie

Abstract:

Delay Tolerant Networks (DTN) which have sufficient state information include trajectory and contact information, to protect routing efficiency. However, state information is dynamic and hard to obtain without a global and/or long-term collection process. To deal with these problems, the internal social features of each node are introduced in the network to perform the routing process. This type of application is motivated from several human contact networks where people contact each other more frequently if they have more social features in common. Two unique processes were developed for this process; social feature extraction and multipath routing. The routing method then becomes a hypercube–based feature matching process. Furthermore, the effectiveness of multipath routing is evaluated and compared to that of single-path routing.

Keywords: Delay tolerant networks, entropy, human contact networks, hyper cubes, multipath Routing, social features.

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Authors: Daiming Wang

Abstract:

In this paper, a neutral impulsive competition system with distributed delays is studied by using Mawhin-s coincidence degree theory and the mean value theorem of differential calculus. Sufficient conditions on the existence of positive periodic solution of the system are obtained.

Keywords: Neutral impulsive delay system, competitive system, coincidence degree, periodic solution, existence.

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Authors: Amir Khalid, B. Manshoor

Abstract:

The mixture formation prior to the ignition process plays as a key element in the diesel combustion. Parametric studies of mixture formation and ignition process in various injection parameter has received considerable attention in potential for reducing emissions. Purpose of this study is to clarify the effects of injection pressure on mixture formation and ignition especially during ignition delay period, which have to be significantly influences throughout the combustion process and exhaust emissions. This study investigated the effects of injection pressure on diesel combustion fundamentally using rapid compression machine. The detail behavior of mixture formation during ignition delay period was investigated using the schlieren photography system with a high speed camera. This method can capture spray evaporation, spray interference, mixture formation and flame development clearly with real images. Ignition process and flame development were investigated by direct photography method using a light sensitive high-speed color digital video camera. The injection pressure and air motion are important variable that strongly affect to the fuel evaporation, endothermic and prolysis process during ignition delay. An increased injection pressure makes spray tip penetration longer and promotes a greater amount of fuel-air mixing occurs during ignition delay. A greater quantity of fuel prepared during ignition delay period thus predominantly promotes more rapid heat release.

Keywords: Mixture Formation, Diesel Combustion, Ignition Process, Spray, Rapid Compression Machine.

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Authors: Yngvar Berg, Omid Mirmotahari

Abstract:

In this paper we ultra low-voltage and high speed CMOS domino logic. For supply voltages below 500mV the delay for a ultra low-voltage NAND2 gate is aproximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch is much less than for conventional CMOS. Differential domino gates for AND/NAND and OR/NOR operation are presented.

Keywords: Low-voltage, high-speed, NAND, NOR, CMOS.

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Authors: B.W. Field

Abstract:

For a variety of safety and economic reasons, engineering undergraduates in Australia have experienced diminishing access to the real hardware that is typically the embodiment of their theoretical studies. This trend will delay the development of practical competence, decrease the ability to model and design, and suppress motivation. The author has attempted to address this concern by creating a software tool that contains both photographic images of real machinery, and sets of graphical modeling 'tools'. Academics from a range of disciplines can use the software to set tutorial tasks, and incorporate feedback comments for a range of student responses. An evaluation of the software demonstrated that students who had solved modeling problems with the aid of the electronic tutor performed significantly better in formal examinations with similar problems. The 2-D graphical diagnostic routines in the Tutor have the potential to be used in a wider range of problem-solving tasks.

Keywords: CAL, graphics, modeling, structural distillation, tutoring.

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Authors: Seyed Saeed Changiz Rezaei, Babak Hossein Khalaj

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As the demand for higher capacity in a cellular environment increases, the cell size decreases. This fact makes the role of suitable handoff algorithms to reduce both number of handoffs and handoff delay more important. In this paper we show that applying the grey prediction technique for handoff leads to considerable decrease in handoff delay with using a small number of handoffs, compared with traditional hystersis based handoff algorithms.

Keywords: Cellular network, Grey prediction, Handoff.

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Authors: H. El-Madbouly

Abstract:

In this paper, genetic algorithm (GA) is proposed for the design of an optimization algorithm to achieve the bandwidth allocation of ATM network. In Broadband ISDN, the ATM is a highbandwidth; fast packet switching and multiplexing technique. Using ATM it can be flexibly reconfigure the network and reassign the bandwidth to meet the requirements of all types of services. By dynamically routing the traffic and adjusting the bandwidth assignment, the average packet delay of the whole network can be reduced to a minimum. M/M/1 model can be used to analyze the performance.

Keywords: Bandwidth allocation, Genetic algorithm, ATMNetwork, packet delay.

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Authors: Sui Xin, Li Chunsheng, Tian Di

Abstract:

Short message integrated distributed monitoring systems (SM-DMS) are growing rapidly in wireless communication applications in various areas, such as electromagnetic field (EMF) management, wastewater monitoring, and air pollution supervision, etc. However, delay in short messages often makes the data embedded in SM-DMS transmit unreliably. Moreover, there are few regulations dealing with this problem in SMS transmission protocols. In this study, based on the analysis of the command and data requirements in the SM-DMS, we developed a processing model for the control center to solve the delay problem in data transmission. Three components of the model: the data transmission protocol, the receiving buffer pool method, and the timer mechanism were described in detail. Discussions on adjusting the threshold parameter in the timer mechanism were presented for the adaptive performance during the runtime of the SM-DMS. This model optimized the data transmission reliability in SM-DMS, and provided a supplement to the data transmission reliability protocols at the application level.

Keywords: Delay, SMS, reliability, distributed monitoringsystem (DMS), wireless communication.

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Authors: Yun Won Chung

Abstract:

The energy consumption of home femto base stations (BSs) can be reduced, by turning off the Wi-Fi radio interface when there is no mobile station (MS) under the coverage of the BSs or MSs do not transmit or receive data packet for long time, especially in late night. In the energy-efficient home femto BSs, if MSs have any data packet to transmit and the Wi-Fi radio interface in off state, MSs wake up the Wi-Fi radio interface of home femto BSs by using additional low power radio interface. In this paper, the performance of the energy-efficient home femto BSs from the aspect of energy consumption and cumulative average delay, and show the effect of various parameters on energy consumption and cumulative average delay. From the results, the tradeoff relationship between energy consumption and cumulative average delay is shown and thus, appropriate operation should be needed to balance the tradeoff.

Keywords: energy consumption, power saving, femto base station.

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Authors: Mayank Shakya, Soundra Pandian. K. K

Abstract:

A linear feedback shift register (LFSR) is proposed which targets to reduce the power consumption from within. It reduces the power consumption during testing of a Circuit Under Test (CUT) at two stages. At first stage, Control Logic (CL) makes the clocks of the switching units of the register inactive for a time period when output from them is going to be same as previous one and thus reducing unnecessary switching of the flip-flops. And at second stage, the LFSR reorders the test vectors by interchanging the bit with its next and closest neighbor bit. It keeps fault coverage capacity of the vectors unchanged but reduces the Total Hamming Distance (THD) so that there is reduction in power while shifting operation.

Keywords: Linear Feedback Shift Register, Total Hamming Distance, Fault Coverage, Control Logic

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Authors: Shilpi Lavania

Abstract:

As the frequency of operation has attained a range of GHz and signal rise time continues to increase interconnect technology is suffering due to various high frequency effects as well as ground bounce problem. In some recent studies a high frequency effect i.e. skin effect has been modeled and its drawbacks have been discussed. This paper strives to make an impression on the advantage side of modeling skin effect for interconnect line. The proposed method has considered a CMOS with RC interconnect. Delay and noise considering ground bounce problem and with skin effect are discussed. The simulation results reveal an advantage of considering skin effect for minimization of ground bounce problem during the working of the model. Noise and delay variations with temperature are also presented.

Keywords: Interconnect, Skin effect, Ground Bounce, Delay, Noise.

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Authors: B. S. Yew , B. L. Ong , R. B. Ahmad

Abstract:

This paper describes the performance of TCP Vegas over the wireless IPv6 network. The performance of TCP Vegas is evaluated using network simulator (ns-2). The simulation experiment investigates how packet spacing affects the network delay, network throughput and network efficiency of TCP Vegas. Moreover, we investigate how the variable FTP packet sizes affect the network performance. The result of the simulation experiment shows that as the packet spacing is implements, the network delay is reduces, network throughput and network efficiency is optimizes. As the FTP packet sizes increase, the ratio of delay per throughput decreases. From the result of experiment, we propose the appropriate packet size in transmitting file transfer protocol application using TCP Vegas with packet spacing enhancement over wireless IPv6 environment in ns-2. Additionally, we suggest the appropriate ratio in determining the appropriate RTT and buffer size in a network.

Keywords: TCP Vegas, Packet Spacing, Packet Size, Wireless IPv6, ns-2

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Authors: Sana Testouri, Karim Saadaoui, Mohamed Benrejeb

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This paper presents a Particle Swarm Optimization (PSO) method for determining the optimal parameters of a first-order controller for TCP/AQM system. The model TCP/AQM is described by a second-order system with time delay. First, the analytical approach, based on the D-decomposition method and Lemma of Kharitonov, is used to determine the stabilizing regions of a firstorder controller. Second, the optimal parameters of the controller are obtained by the PSO algorithm. Finally, the proposed method is implemented in the Network Simulator NS-2 and compared with the PI controller.

Keywords: AQM, first-order controller, time delay, stability, PSO.

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Authors: Mohammad Taghi Darvishi, Samad Kheybari

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In this paper, the dynamics of a system of two van der Pol oscillators with delayed position and velocity is studied. We provide an approximate solution for this system using parameterexpansion method. Also, we obtain approximate values for frequencies of the system. The parameter-expansion method is more efficient than the perturbation method for this system because the method is independent of perturbation parameter assumption.

Keywords: Parameter-expansion method, coupled van der pol oscillator, time-delay system.

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Authors: Abolhassan Razminia, Mohammad-Ali Sadrnia

Abstract:

Chua’s circuit is one of the most important electronic devices that are used for Chaos and Bifurcation studies. A central role of secure communication is devoted to it. Since the adaptive control is used vastly in the linear systems control, here we introduce a new trend of application of adaptive method in the chaos controlling field. In this paper, we try to derive a new adaptive control scheme for Chua’s circuit controlling because control of chaos is often very important in practical operations. The novelty of this approach is for sake of its robustness against the external perturbations which is simulated as an additive noise in all measured states and can be generalized to other chaotic systems. Our approach is based on Lyapunov analysis and the adaptation law is considered for the feedback gain. Because of this, we have named it NAFT (Nonlinear Adaptive Feedback Technique). At last, simulations show the capability of the presented technique for Chua’s circuit.

Keywords: Chaos, adaptive control, nonlinear control, Chua's circuit.

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Authors: F. Khaber, K. Zehar, A. Hamzaoui

Abstract:

In this paper, we introduce a robust state feedback controller design using Linear Matrix Inequalities (LMIs) and guaranteed cost approach for Takagi-Sugeno fuzzy systems. The purpose on this work is to establish a systematic method to design controllers for a class of uncertain linear and non linear systems. Our approach utilizes a certain type of fuzzy systems that are based on Takagi-Sugeno (T-S) fuzzy models to approximate nonlinear systems. We use a robust control methodology to design controllers. This method not only guarantees stability, but also minimizes an upper bound on a linear quadratic performance measure. A simulation example is presented to show the effectiveness of this method.

Keywords: Takagi-Sugeno fuzzy model, state feedback, linear matrix inequalities, robust stability.

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Authors: M. Shakir Saat, M. Noh Ahmad, Dr, Amat Amir

Abstract:

A cart-ball system is a challenging system from the control engineering point of view. This is due to the nonlinearities, multivariable, and non-minimum phase behavior present in this system. This paper is concerned with the problem of modeling and control of such system. The objective of control strategy is to place the cart at a desired position while balancing the ball on the top of the arc-shaped track fixed on the cart. A State-Feedback Controller (SFC) with a pole-placement method will be designed in order to control the system. At first, the mathematical model of a cart-ball system in the state-space form is developed. Then, the linearization of a model will be established in order to design a SFC. The integral control strategy will be performed as to control the cart position of a system. Simulation work is then performed using MATLAB/SIMULINK software in order to study the performance of SFC when applied to the system.

Keywords: Cart-Ball System, Integral Control, Pole-PlacementMethod, State-Feedback Controller.

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Authors: Caspar von Seckendorff, Eldar Sultanow

Abstract:

Many studies have shown that parallelization decreases efficiency [1], [2]. There are many reasons for these decrements. This paper investigates those which appear in the context of parallel data integration. Integration processes generally cannot be allocated to packages of identical size (i. e. tasks of identical complexity). The reason for this is unknown heterogeneous input data which result in variable task lengths. Process delay is defined by the slowest processing node. It leads to a detrimental effect on the total processing time. With a real world example, this study will show that while process delay does initially increase with the introduction of more nodes it ultimately decreases again after a certain point. The example will make use of the cloud computing platform Hadoop and be run inside Amazon-s EC2 compute cloud. A stochastic model will be set up which can explain this effect.

Keywords: Process delay, speedup, efficiency, parallel computing, data integration, E-Commerce, Amazon Elastic Compute Cloud (EC2), Hadoop, Nutch.

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Authors: Venkatesh C., K. Shanti Swarup

Abstract:

This paper investigates the impact on operating time delay and relay maloperation when 1st,2nd and 3rd order analog antialiasing filters are used in numerical distance protection. RC filter with cut-off frequency 90 Hz is used. Simulations are carried out for different SIR (Source to line Impedance Ratio), load, fault type and fault conditions using SIMULINK, where the voltage and current signals are fed online to the developed numerical distance relay model. Matlab is used for plotting the impedance trajectory. Investigation results shows that, about 75 % of the simulated cases, numerical distance relay operating time is not increased even-though there is a time delay when higher order filters are used. Relay maloperation (selectivity) also reduces (increases) when higher order filters are used in numerical distance protection.

Keywords: Antialiasing, capacitive voltage transformers, delay estimation, discrete Fourier transform (DFT), distance measurement, low-pass filters, source to line impedance ratio (SIR), protective relaying.

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Authors: Farzana Yasmeen, Md. Nurul Huda, Md. Enamul Haque, Michihiro Aoki, Shigeki Yamada

Abstract:

Delay-Tolerant Networks (DTNs) are sparse, wireless networks where disconnections are common due to host mobility and low node density. The Message Ferrying (MF) scheme is a mobilityassisted paradigm to improve connectivity in DTN-like networks. A ferry or message ferry is a special node in the network which has a per-determined route in the deployed area and relays messages between mobile hosts (MHs) which are intermittently connected. Increased contact opportunities among mobile hosts and the ferry improve the performance of the network, both in terms of message delivery ratio and average end-end delay. However, due to the inherent mobility of mobile hosts and pre-determined periodicity of the message ferry, mobile hosts may often -miss- contact opportunities with a ferry. In this paper, we propose the combination of stationary ferry access points (FAPs) with MF routing to increase contact opportunities between mobile hosts and the MF and consequently improve the performance of the DTN. We also propose several placement models for deploying FAPs on MF routes. We evaluate the performance of the FAP placement models through comprehensive simulation. Our findings show that FAPs do improve the performance of MF-assisted DTNs and symmetric placement of FAPs outperforms other placement strategies.

Keywords: Service infrastructure, delay-tolerant network, messageferry routing, placement models.

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Authors: Nan-Chyuan Tsai, Din-Chang Chen, Rong-Mao Lee, Bai-Lu Wang

Abstract:

This paper presents how the real-time chatter prevention can be realized by feedback of acoustic cutting signal, and the efficacy of the proposed adaptive spindle speed tuning algorithm is verified by intensive experimental simulations. A pair of microphones, perpendicular to each other, is used to acquire the acoustic cutting signal resulting from milling chatter. A real-time feedback control loop is constructed for spindle speed compensation so that the milling process can be ensured to be within the stability zone of stability lobe diagram. Acoustic Chatter Signal Index (ACSI) and Spindle Speed Compensation Strategy (SSCS) are proposed to quantify the acoustic signal and actively tune the spindle speed respectively. By converting the acoustic feedback signal into ACSI, an appropriate Spindle Speed Compensation Rate (SSCR) can be determined by SSCS based on real-time chatter level or ACSI. Accordingly, the compensation command, referred to as Added-On Voltage (AOV), is applied to increase/decrease the spindle motor speed. By inspection on the precision and quality of the workpiece surface after milling, the efficacy of the real-time chatter prevention strategy via acoustic signal feedback is further assured.

Keywords: Chatter compensation, Stability lobes, Non-invasivemeasurement.

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Authors: P.Ramanathan, P.T.Vanathi

Abstract:

Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and the growing needs of portable devices, low-power and highperformance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, fan-out and interconnect count of logic circuits. In this paper, a new architecture for performing 8-bit, 16-bit and 32-bit Parallel Prefix addition is proposed. The proposed prefix adder structures is compared with several classical adders of same bit width in terms of power, delay and number of computational nodes. The results reveal that the proposed structures have the least power delay product when compared with its peer existing Prefix adder structures. Tanner EDA tool was used for simulating the adder designs in the TSMC 180 nm and TSMC 130 nm technologies.

Keywords: Parallel Prefix Adder (PPA), Dot operator, Semi-Dotoperator, Complementary Metal Oxide Semiconductor (CMOS), Odd-dot operator, Even-dot operator, Odd-semi-dot operator andEven-semi-dot operator.

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Authors: Santirat Nansaarng, Sittichai Kaewkuekool, Supreeya Siripattanakunkajorn

Abstract:

The purpose of this research was to study the inspector performance by using computer based training (CBT). Visual inspection task was printed circuit board (PCB) simulated on several types of defects. Subjects were 16 undergraduate randomly selected from King Mongkut-s University of Technology Thonburi and test for 20/20. Then, they were equally divided on performance into two groups (control and treatment groups) and were provided information before running the experiment. Only treatment group was provided feedback information after first experiment. Results revealed that treatment group was showed significantly difference at the level of 0.01. The treatment group showed high percentage on defects detected. Moreover, the attitude of inspectors on using the CBT to inspection was showed on good. These results have been showed that CBT could be used for training to improve inspector performance.

Keywords: Training, Feedback, Computer based Training (CBT)

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Authors: Guo-Ming Sung, Naga Raju Naik R.

Abstract:

Paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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