Search results for: CMOS technology

Authors: H. Asiaban, E. Farshidi

Abstract:

This paper presents a new true RMS-to-DC converter circuit based on a square-root-domain squarer/divider. The circuit is designed by employing up-down translinear loop and using of MOSFET transistors that operate in strong inversion saturation region. The converter offer advantages of two-quadrant input current, low circuit complexity, low supply voltage (1.2V) and immunity from the body effect. The circuit has been simulated by HSPICE. The simulation results are seen to conform to the theoretical analysis and shows benefits of the proposed circuit.

Keywords: Current-mode, squarer/divider, low-pass filter, converter, translinear loop, RMS-to-DC.

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Authors: S. Douss, F. Touati, M. Loulou

Abstract:

A design flow of multi-standard down-conversion CMOS mixers for three modern standards: Global System Mobile, Digital Enhanced Cordless Telephone and Universal Mobile Telecommunication Systems is presented. Three active mixer-s structures are studied. The first is based on the Gilbert cell which gives a tolerable noise figure and linearity with a low conversion gain. The second and third structures use the current bleeding and charge injection techniques in order to increase the conversion gain. An improvement of about 2 dB of the conversion gain is achieved without a considerable degradation of the other characteristics. The models used for noise figure, conversion gain and IIP3 used are studied. This study describes the nature of trade-offs inherent in such structures and gives insights that help in identifying which structure is better for given conditions.

Keywords: Active mixer, Radio-frequency transceiver, Multistandardfront end, Gilbert cell, current bleeding, charge injection.

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Authors: Hassan Faraji Baghtash

Abstract:

In this paper, a low voltage high performance current mirror is presented. Its most important specifications, which are improved in this work, are analyzed and formulated proving that it has such outstanding merits as: Very low input resistance of 26mΩ, very wide current dynamic range of 8 decades from 10pA to 1mA (160dB) together with an extremely low current copy error of less than 0.6ppm, and very low input and output voltages. Furthermore, the proposed current mirror bandwidth is 944MHz utilizing very low power consumption (267μW) and transistors count. HSPICE simulation results are performed using TSMC 0.18μm CMOS technology utilizing 1.8V single power supply, confirming the theoretically proved outstanding performance of the proposed current mirror. Monte Carlo simulation of its most important parameter is also examined showing its sufficiently resistance against technology process variations.

Keywords: Current mirror/source, high accuracy, low voltage, wide dynamic range.

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Authors: S. Abdollahi Pour, M. Saneei

Abstract:

This paper propose a new circuit design which monitor total leakage current during standby mode and generates the optimal reverse body bias voltage, by using the adaptive body bias (ABB) technique to compensate die-to-die parameter variations. Design details of power monitor are examined using simulation framework in 65nm and 32nm BTPM model CMOS process. Experimental results show the overhead of proposed circuit in terms of its power consumption is about 10 μW for 32nm technology and about 12 μW for 65nm technology at the same power supply voltage as the core power supply. Moreover the results show that our proposed circuit design is not far sensitive to the temperature variations and also process variations. Besides, uses the simple blocks which offer good sensitivity, high speed, the continuously feedback loop.

Keywords: leakage current, leakage power monitor, body biasing, low power

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Authors: Mohsen Bagheri, Ahmad Afifi

Abstract:

This paper presents a new method for read out of the piezoresistive accelerometer sensors. The circuit works based on Instrumentation amplifier and it is useful for reducing offset In Wheatstone Bridge. The obtained gain is 645 with 1μv/°c Equivalent drift and 1.58mw power consumption. A Schmitt trigger and multiplexer circuit control output node. a high speed counter is designed in this work .the proposed circuit is designed and simulated In 0.18μm CMOS technology with 1.8v power supply.

Keywords: Piezoresistive accelerometer, zero offset, Schmitt trigger, bidirectional reversible counter

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Authors: Yeon-kug Moon, Kang-Yoon Lee, Yun-Jae Won, Seung-Ok Lim

Abstract:

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable gain amplifier (PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance (Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of 0.19mm2.

Keywords: component ; Channel selection filters, DC offset, programmable gain amplifier, tuning circuit

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Authors: Kimberly Jane S. Uy, Patricia Angela Reyes-Abu, Wen Yaw Chung

Abstract:

A high precision temperature insensitive current and voltage reference generator is presented. It is specifically developed for temperature compensated oscillator. The circuit, designed using MXIC 0.5um CMOS technology, has an operating voltage that ranges from 2.6V to 5V and generates a voltage of 1.21V and a current of 6.38 ӴA. It exhibits a variation of ±0.3nA for the current reference and a stable output for voltage reference as the temperature is varied from 0°C to 70°C. The power supply rejection ratio obtained without any filtering capacitor at 100Hz and 10MHz is -30dB and -12dB respectively.

Keywords: Current reference, voltage reference, threshold voltage, temperature compensation, mobility.

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Authors: Lei Yao, Jia Hao Cheong, Rui-Feng Xue, Minkyu Je

Abstract:

A closed-loop controlled wireless power transmission circuit block for implantable biomedical applications is described in this paper. The circuit consists of one front-end rectifier, power management sub-block including bandgap reference and low drop-out regulators (LDOs) as well as transmission power detection / feedback circuits. Simulation result shows that the front-end rectifier achieves 80% power efficiency with 750-mV single-end peak-to-peak input voltage and 1.28-V output voltage under load current of 4 mA. The power management block can supply 1.8mA average load current under 1V consuming only 12μW power, which is equivalent to 99.3% power efficiency. The wireless power transmission block described in this paper achieves a maximum power efficiency of 80%. The wireless power transmission circuit block is designed and implemented using UMC 65-nm CMOS/RF process. It occupies 1 mm × 1.2 mm silicon area.

Keywords: Implantable biomedical devices, wireless power transfer, LDO, rectifier, closed-loop power control

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Authors: Padmanabhan Balasubramanian, Karthik Anantha

Abstract:

Structural representation and technology mapping of a Boolean function is an important problem in the design of nonregenerative digital logic circuits (also called combinational logic circuits). Library aware function manipulation offers a solution to this problem. Compact multi-level representation of binary networks, based on simple circuit structures, such as AND-Inverter Graphs (AIG) [1] [5], NAND Graphs, OR-Inverter Graphs (OIG), AND-OR Graphs (AOG), AND-OR-Inverter Graphs (AOIG), AND-XORInverter Graphs, Reduced Boolean Circuits [8] does exist in literature. In this work, we discuss a novel and efficient graph realization for combinational logic circuits, represented using a NAND-NOR-Inverter Graph (NNIG), which is composed of only two-input NAND (NAND2), NOR (NOR2) and inverter (INV) cells. The networks are constructed on the basis of irredundant disjunctive and conjunctive normal forms, after factoring, comprising terms with minimum support. Construction of a NNIG for a non-regenerative function in normal form would be straightforward, whereas for the complementary phase, it would be developed by considering a virtual instance of the function. However, the choice of best NNIG for a given function would be based upon literal count, cell count and DAG node count of the implementation at the technology independent stage. In case of a tie, the final decision would be made after extracting the physical design parameters. We have considered AIG representation for reduced disjunctive normal form and the best of OIG/AOG/AOIG for the minimized conjunctive normal forms. This is necessitated due to the nature of certain functions, such as Achilles- heel functions. NNIGs are found to exhibit 3.97% lesser node count compared to AIGs and OIG/AOG/AOIGs; consume 23.74% and 10.79% lesser library cells than AIGs and OIG/AOG/AOIGs for the various samples considered. We compare the power efficiency and delay improvement achieved by optimal NNIGs over minimal AIGs and OIG/AOG/AOIGs for various case studies. In comparison with functionally equivalent, irredundant and compact AIGs, NNIGs report mean savings in power and delay of 43.71% and 25.85% respectively, after technology mapping with a 0.35 micron TSMC CMOS process. For a comparison with OIG/AOG/AOIGs, NNIGs demonstrate average savings in power and delay by 47.51% and 24.83%. With respect to device count needed for implementation with static CMOS logic style, NNIGs utilize 37.85% and 33.95% lesser transistors than their AIG and OIG/AOG/AOIG counterparts.

Keywords: AND-Inverter Graph, OR-Inverter Graph, DirectedAcyclic Graph, Low power design, Delay optimization.

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Authors: Ankit Mitra

Abstract:

Speed, power consumption and area, are some of the most important factors of concern in modern day memory design. As we move towards Deep Sub-Micron Technologies, the problems of leakage current, noise and cell stability due to physical parameter variation becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port SRAM Cell with Dual Threshold Voltage and characterized it in terms of read and write delay, read and write noise margins, Data Retention Voltage and Leakage Current. Read Decoupling improves the Read Noise Margin and static power dissipation is reduced by using Dual-V_t transistors. The results obtained are compared with existing 6T, 8T, 9T SRAM Cells, which shows the superiority of the proposed design. The Cell is designed and simulated in TSPICE using 90nm CMOS process.

Keywords: CMOS, Dual-Port, Data Retention Voltage, 8T SRAM, Leakage Current, Noise Margin, Loop-cutting, Single-ended.

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Authors: O. Hashemipour, S. G. Nabavi

Abstract:

A high-linearity and high-speed current-mode sampleand- hold circuit is designed and simulated using a 0.25μm CMOS technology. This circuit design is based on low voltage and it utilizes a fully differential circuit. Due to the use of only two switches the switch related noise has been reduced. Signal - dependent -error is completely eliminated by a new zero voltage switching technique. The circuit has a linearity error equal to ±0.05μa, i.e. 12-bit accuracy with a ±160 μa differential output - input signal frequency of 5MHZ, and sampling frequency of 100 MHZ. Third harmonic is equal to –78dB.

Keywords: Zero-voltage-technique, MOS-resistor, OTA, Feedback-resistor.

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Authors: Jun Sung Go, Jong Kang Park, Jong Tae Kim

Abstract:

As semi-conductor manufacturing technology evolves; the single event transient problem becomes more significant issue. Single event transient has a critical impact on both combinational and sequential logic circuits, so it is important to evaluate the soft error tolerance of the circuits at the design stage. In this paper, we present a soft error detecting simulation using scan chain. The simulation model generates a single event transient randomly in the circuit, and detects the soft error during the execution of the test patterns. We verified this model by inserting a scan chain in an 8051 microprocessor using 65 nm CMOS technology. While the test patterns generated by ATPG program are passing through the scan chain, we insert a single event transient and detect the number of soft errors per sub-module. The experiments show that the soft error rates per cell area of the SFR module is 277% larger than other modules.

Keywords: Scan chain, single event transient, soft error, 8051 processor.

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Authors: Omid Mirmotahari, Yngvar Berg, Ahmad Habibizad Navin

Abstract:

Reversible logic is becoming more and more prominent as the technology sets higher demands on heat, power, scaling and stability. Reversible gates are able at any time to "undo" the current step or function. Multiple-valued logic has the advantage of transporting and evaluating higher bits each clock cycle than binary. Moreover, we demonstrate in this paper, combining these disciplines we can construct powerful multiple-valued reversible logic structures. In this paper a reversible block implemented by pseudo floatinggate can perform AD-function and a DA-function as its reverse application.

Keywords: Reversible logic, bi-directional, Pseudo floating-gate(PFG), multiple-valued logic (MVL).

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Authors: Yasir Mahmood Qureshi

Abstract:

This paper presents the design and layout of a two stage, high speed operational amplifiers using standard 0.35um CMOS technology. The design procedure involves designing the bias circuit, the differential input pair, and the gain stage using CAD tools. Both schematic and layout of the operational amplifier along with the comparison in the results of the two has been presented. The operational amplifier designed, has a gain of 93.51db at low frequencies. It has a gain bandwidth product of 55.07MHz, phase margin of 51.9º and a slew rate of 22v/us for a load of capacitor of 10pF.

Keywords: Gain bandwidth product, Operational Amplifier, phase margin, slew rate.

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Authors: H. A. Majid, N. Razali, M. S. Sulaiman, A. K. A'ain

Abstract:

A new interface circuit for capacitive sensor is presented. This paper presents the design and simulation of soil moisture capacitive sensor interface circuit based on phase differential technique. The circuit has been designed and fabricated using MIMOS- 0.35"m CMOS technology. Simulation and test results show linear characteristic from 36 – 52 degree phase difference, representing 0 – 100% in soil moisture level. Test result shows the circuit has sensitivity of 0.79mV/0.10 phase difference, translating into resolution of 10% soil moisture level.

Keywords: Capacitive sensor, interface, phase differential.

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Authors: Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou

Abstract:

This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm² and dissipates 233.5 mW at maximal operating frequency of 250 MHz.

Keywords: Reconfigurable, fast Fourier transform, single-path delay feedback, 3GPP-LTE.

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Authors: Hassan Faraji Baghtash

Abstract:

A high-speed current mirror with low-power method of adjusting current gain is presented. The current mirror provides continuous gain adjustment; yet, its gain can simply be programmed digitally, as well. The structure features the ever interesting merits of linear-in-dB gain control scheme and low power/voltage operation. The performance of proposed structure is verified through the simulation in TSMC 0.18 µm CMOS Technology. The proposed tunable gain current mirror structure draws only 18 µW from 0.9 V power supply and can operate at high frequencies up to 550 MHz in the worst case condition of maximum gain setting.

Keywords: Current mirror, current mode, low power, low voltage, tunable circuit, variable current amplifier.

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Authors: T. Vigneswaran, B. Mukundhan, P. Subbarami Reddy

Abstract:

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.

Keywords: Arithmetic circuit, full adder, multiplier, low power, very Large-scale integration (VLSI).

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Authors: Yavar Safaei Mehrabani, Mehdi Hosseinzadeh

Abstract:

As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo 2n+1 adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set (2n-1,2n, 2n+1). In this manuscript we have introduced novel binary representation to the design of modulo 2n+1 adder. VLSI realization of proposed architecture under 180 nm full static CMOS technology reveals its superiority in terms of area, power consumption and power-delay product (PDP) against several peer existing structures.

Keywords: Computer arithmetic, modulo 2n+1 adders, Residue Number System (RNS), VLSI.

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Authors: Rishikesh Pandey, Maneesha Gupta

Abstract:

A new low-voltage floating gate MOSFET (FGMOS) based squarer using square law characteristic of the FGMOS is proposed in this paper. The major advantages of the squarer are simplicity, rail-to-rail input dynamic range, low total harmonic distortion, and low power consumption. The proposed circuit is biased without body effect. The circuit is designed and simulated using SPICE in 0.25μm CMOS technology. The squarer is operated at the supply voltages of ±0.75V . The total harmonic distortion (THD) for the input signal 0.75Vpp at 25 KHz, and maximum power consumption were found to be less than 1% and 319μW respectively.

Keywords: Analog signal processing, floating gate MOSFETs, low-voltage, Spice, squarer.

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Authors: Arash Azizi-Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, Ali Barati

Abstract:

The energy consumption and delay in read/write operation of conventional SRAM is investigated analytically as well as by simulation. Explicit analytical expressions for the energy consumption and delay in read and write operation as a function of device parameters and supply voltage are derived. The expressions are useful in predicting the effect of parameter changes on the energy consumption and speed as well as in optimizing the design of conventional SRAM. HSPICE simulation in standard 0.25μm CMOS technology confirms precision of analytical expressions derived from this paper.

Keywords: Read energy consumption, write energy consumption, read delay, write delay.

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Authors: Il-Do Jeong, Hang-Geun Jeong

Abstract:

This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in range without using the reference clock. The proposed CDR was implemented using a 1/4-rate bang-bang type phase detector (PD) and a ring voltage controlled oscillator (VCO). The CDR circuit has been fabricated in a standard 0.18 CMOS technology. It occupies an active area of 1 x 1 and consumes 90 mW from a single 1.8V supply.

Keywords: Clock and data recovery, 1/4-rate frequency detector, 1/4-rate phase detector.

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Authors: Krzysztof Wawryn, Robert Suszyński, Bogdan Strzeszewski

Abstract:

This paper presents two prototypes of low power low voltage current mode 9 bit pipelined a/d converters. The first and the second converters are configured of 1.5 bit and 2.5 bit stages, respectively. The a/d converter structures are composed of current mode building blocks and final comparator block which converts the analog current signal into digital voltage signal. All building blocks have been designed in CMOS AMS 0.35μm technology, then simulated to verify proposed concept. The performances of both converters are compared to performances of known current mode and voltage mode switched capacitance converter structures. Low power consumption and small chip area are advantages of the proposed converters.

Keywords: Pipelined converter, a/d converter, low power, lowvoltage, current mode.

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Authors: Jörg Lenhardt, Wolfram Schiffmann, Jörg Keller

Abstract:

While the feature sizes of recent Complementary Metal Oxid Semiconductor (CMOS) devices decrease the influence of static power prevails their energy consumption. Thus, power savings that benefit from Dynamic Frequency and Voltage Scaling (DVFS) are diminishing and temporal shutdown of cores or other microchip components become more worthwhile. A consequence of powering off unused parts of a chip is that the relative difference between idle and fully loaded power consumption is increased. That means, future chips and whole server systems gain more power saving potential through power-aware load balancing, whereas in former times this power saving approach had only limited effect, and thus, was not widely adopted. While powering off complete servers was used to save energy, it will be superfluous in many cases when cores can be powered down. An important advantage that comes with that is a largely reduced time to respond to increased computational demand. We include the above developments in a server power model and quantify the advantage. Our conclusion is that strategies from datacenters when to power off server systems might be used in the future on core level, while load balancing mechanisms previously used at core level might be used in the future at server level.

Keywords: Power efficiency, static power consumption, dynamic power consumption, CMOS.

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Authors: Lv Xiaopeng, Bian Qiang, Yue Suge

Abstract:

A fully on-chip low drop-out (LDO) voltage regulator with 100pF output load capacitor is presented. A novel frequency compensation scheme using current buffer is adopted to realize single dominant pole within the unit gain frequency of the regulation loop, the phase margin (PM) is at least 50 degree under the full range of the load current, and the power supply rejection (PSR) character is improved compared with conventional Miller compensation. Besides, the differentiator provides a high speed path during the load current transient. Implemented in 0.18μm CMOS technology, the LDO voltage regulator provides 100mA load current with a stable 1.8V output voltage consuming 80μA quiescent current.

Keywords: capacitor-less LDO, frequency compensation, transient response, power supply rejection

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Authors: Padmanabhan Balasubramanian, C. Ardil

Abstract:

In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(mj) ∪ D(mk) = { } and therefore, we have | D(mj) ∪ D(mk) | = 0 [19]. Similarly, D(Mj) ∪ D(Mk) = { } and hence | D(Mj) ∪ D(Mk) | = 0. Here, 'mk' and 'Mk' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form. We have opted for algebraic factorization of the Reed-Muller (RM) form and its different variants, using the factorization rules of [1], as it is simple and requires much less CPU execution time compared to Boolean factorization operations. This technique has enabled us to greatly reduce the literal count as well as the gate count needed for such RM realizations, which are generally prone to consuming more cells and subsequently more power consumption. However, this leads to a drawback in terms of the design-for-test attribute associated with the various RM forms. Though we still preserve the definition of those forms viz. realizing such functionality with only select types of logic gates (AND gate and XOR gate), the structural integrity of the logic levels is not preserved. This would consequently alter the testability properties of such circuits i.e. it may increase/decrease/maintain the same number of test input vectors needed for their exhaustive testability, subsequently affecting their generalized test vector computation. We do not consider the issue of design-for-testability here, but, instead focus on the power consumption of the final logic implementation, after realization with a conventional CMOS process technology (0.35 micron TSMC process). The quality of the resulting circuits evaluated on the basis of an established cost metric viz., power consumption, demonstrate average savings by 26.79% for the samples considered in this work, besides reduction in number of gates and input literals by 39.66% and 12.98% respectively, in comparison with other factored RM forms.

Keywords: Reed-Muller forms, Logic function, Hammingdistance, Algebraic factorization, Low power design.

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Authors: Seongykyoon Jeong, Sungki Lee, Jaeyun Kim, Seunghun Oh, Kiho Kwak

Abstract:

The purpose of study is to demonstrate how the characteristics of technology and the process required for development of technology affect technology transfer from public organisations to industry on the technology level. In addition, using the advantage of the analytic level and the novel means of measuring technology convergence, we examine the characteristics of converging technologies as compared to non-converging technologies in technology transfer process. In sum, our study finds that a technology from the public sector is likely to be transferred when its readiness level is closer to generation of profit, when its stage of life cycle is early and when its economic values is high. Our findings also show that converging technologies are less likely to be transferred.

Keywords: Interdisciplinary, Technology transfer, Technology convergence.

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Authors: Hasmayadi Abdul Majid, Rohana Musa

Abstract:

This paper presents the development of a 38.5 kS/s 10-bit low power SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and SAR digital logic to create 10 effective bits while consuming less than 7.8 mW with a 3.3 V power supply.

Keywords: Successive Approximation Register Analog-to- Digital Converter, SAR ADC, Resistive DAC.

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Authors: S. Kumaravel, B. Venkataramani

Abstract:

In the literature, Improved Recycling Folded Cascode (IRFC) Operational Transconductance Amplifier (OTA) is proposed for enhancing the DC gain and the Unity Gain Bandwidth (UGB) of the Recycling Folded Cascode (RFC) OTA. In this paper, an enhanced IRFC (EIRFC) OTA which uses positive feedback at the cascode node is proposed for enhancing the differential mode (DM) gain without changing the unity gain bandwidth (UGB) and lowering the Common mode (CM) gain. For the purpose of comparison, IRFC and EIRFC OTAs are implemented using UMC 90nm CMOS technology and studied through simulation. From the simulation, it is found that the DM gain and CM gain of EIRFC OTA is higher by 6dB and lower by 38dB respectively, compared to that of IRFC OTA for the same power and area. The slew rate of EIRFC OTA is also higher by a factor of 1.5.

Keywords: Cascode Amplifier, CMRR, gm/ID Methodology, Recycling, Slew Rate.

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Authors: Kah-Hyong Chang, Xin Liu, Jia Hao Cheong, Saisundar Sankaranarayanan, Dexing Pang, Hongzhao Zheng

Abstract:

A digital baseband Application-Specific Integrated Circuit (ASIC) (yclic Redundancy Checkis developed for a microchip transponder to transmit signals and temperature levels from biomedical monitoring devices. The transmission protocol is adapted from the ISO/IEC 11784/85 standard. The module has a decimation filter that employs only a single adder-subtractor in its datapath. The filtered output is coded with cyclic redundancy check and transmitted through backscattering Load Shift Keying (LSK) modulation to a reader. Fabricated using the 0.18-μm CMOS technology, the module occupies 0.116 mm² in chip area (digital baseband: 0.060 mm², decimation filter: 0.056 mm²), and consumes a total of less than 0.9 μW of power (digital baseband: 0.75 μW, decimation filter: 0.14 μW).

Keywords: Biomedical sensor, decimation filter, Radio Frequency Integrated Circuit (RFIC) baseband, temperature sensor.

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