As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo 2n+1 adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set (2n-1,2n, 2n+1). In this manuscript we have introduced novel binary representation to the design of modulo 2n+1 adder. VLSI realization of proposed architecture under 180 nm full static CMOS technology reveals its superiority in terms of area, power consumption and power-delay product (PDP) against several peer existing structures.<\/p>\r\n","references":"[1] G. Lakhani, \"VLSI design of modulo adders\/subtractors,\" IEEE Int.\r\nconf. on Computer Design, ICCD'92, October 1992, PP. 68-71.\r\n[2] W. L. Freking, and K. K. Parhi, \"Low-Power FIR digital filters using\r\nresidue arithmetic,\" proc. of 31th Asilomar Conference on Signals,\r\nSystems, and Computers, Vol. 1, November 1997, PP. 739-43.\r\n[3] F. Taylor, \"A Single Modulus ALU for Signal Processing,\" IEEE Trans.\r\non Acoustics, Speech, Signal Processing, Vol. 33, 1985, PP. 1302-1315.\r\n[4] M. Bhardwaj, and B. Ljusanin, \"The Renaissance-A Residue Number\r\nSystem Based Vector Co-Processor for DSP Dominated Embedded\r\nASICs,\" Proc. of Asimolar conference on Signals, Systems, and\r\ncomputers, 1998, PP. 202-207.\r\n[5] P. G. Fernandez, A. Garcia, J. Ramirez, L. Parrilla, and A. Lioris, \"A\r\nRNS-Based Matrix-Vector-Multiply FCT architecture for DCT\r\ncomputation,\" Proc. 43rd IEEE Midwest Symposium On circuits and\r\nsystems, 2000, PP. 350-353.\r\n[6] E. Kinoshita, and K. Lee, \"A Residue Arithmetic Extension for Reliable\r\nScientific Computation,\" IEEE Trans. on Computers, Vol. 46, No. 2,\r\n1997, PP. 129-138.\r\n[7] V. Paliouras, and T. Stouraitis, \"Novel High-Radix Residue Number\r\nSystem Architectures,\" IEEE Trans. circuits SYST. II, Vol. 47, No. 10,\r\nOctober 2000, PP. 1059-1073.\r\n[8] A. S. Molahosseini, and K. Navi, \"New arithmetic Residue to Binary\r\nconverters,\" International Journal of Computer Sciences and\r\nEngineering Systems, Vol. 1, No. 4, October 2007, PP. 295-299.\r\n[9] B. Cao, C. H. Chang, and T. Srikanthan, \"A residue-to-binary converter\r\nfor a new 5-moduli set,\" IEEE Trans. circuits SYST. \u00f0\u00e5, Vol. 54, No. 5,\r\n2007, PP. 1041-1049.\r\n[10] A. Curiger, \"VLSI Architectures for computations in finite rings and\r\nfields,\" ph. d. thesis, Swiss federal institute of technology, 1993.\r\n[11] R. Zimmermann, and et al., \"A 177Mb\/s VLSI implementation of the\r\ninternational data encryption algorithm,\" IEEE J. solid-state circuits,\r\nVol. 29, No. 3, 1994, PP. 303-307.\r\n[12] M. Bayoumi, and G. Jullien, \"A VLSI Implementation of Residue\r\nAdders,\" IEEE Trans. Circuits and systems, Vol. 34, 1987, PP. 284-288.\r\n[13] M. Dugdale, \"VLSI Implementation of Residue Adders based on binary\r\nAdders,\" IEEE Trans. circuits SYST. II, Vol. 39, No. 5, 1992, PP. 325-\r\n329.\r\n[14] A. A. Hiasat, \"High-speed and Reduced Area Modular Adder structures\r\nfor RNS,\" IEEE Trans. on Computers, Vol. 51, No. 1, 2002, PP. 84-89.\r\n[15] C. Efstathiou, and H. T. Vergos, \"Fast Parallel-Prefix modulo 2n+1\r\nAdder,\" IEEE Trans. on Computers, Vol. 53, No. 9, 2004, PP. 1211-\r\n1216.\r\n[16] G. Jaberipur, and B. Parhami, \"Unified Approach to the design of\r\nModulo-(2n\u252c\u25921) Adders Based on Signed-LSB Representation of\r\nResidues,\" in proc. of the 19th IEEE Symposium on computer\r\narithmetic, June 2009, PP. 57-64.","publisher":"World Academy of Science, Engineering and Technology","index":"Open Science Index 56, 2011"}