@article{(Open Science Index):https://publications.waset.org/pdf/3344,
	  title     = {A 3.125Gb/s Clock and Data Recovery Circuit Using 1/4-Rate Technique},
	  author    = {Il-Do Jeong and  Hang-Geun Jeong},
	  country	= {},
	  institution	= {},
	  abstract     = {This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in range without using the reference clock. The proposed CDR was implemented using a 1/4-rate bang-bang type phase detector (PD) and a ring voltage controlled oscillator (VCO). The CDR circuit has been fabricated in a standard 0.18 CMOS technology. It occupies an active area of 1 x 1 and consumes 90 mW from a single 1.8V supply.
},
	    journal   = {International Journal of Electrical and Computer Engineering},
	  volume    = {1},
	  number    = {7},
	  year      = {2007},
	  pages     = {1105 - 1107},
	  ee        = {https://publications.waset.org/pdf/3344},
	  url   	= {https://publications.waset.org/vol/7},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 7, 2007},
	}