Search results for: Cascode Amplifier

Authors: S. Kumaravel, B. Venkataramani

Abstract:

In the literature, Improved Recycling Folded Cascode (IRFC) Operational Transconductance Amplifier (OTA) is proposed for enhancing the DC gain and the Unity Gain Bandwidth (UGB) of the Recycling Folded Cascode (RFC) OTA. In this paper, an enhanced IRFC (EIRFC) OTA which uses positive feedback at the cascode node is proposed for enhancing the differential mode (DM) gain without changing the unity gain bandwidth (UGB) and lowering the Common mode (CM) gain. For the purpose of comparison, IRFC and EIRFC OTAs are implemented using UMC 90nm CMOS technology and studied through simulation. From the simulation, it is found that the DM gain and CM gain of EIRFC OTA is higher by 6dB and lower by 38dB respectively, compared to that of IRFC OTA for the same power and area. The slew rate of EIRFC OTA is also higher by a factor of 1.5.

Keywords: Cascode Amplifier, CMRR, gm/ID Methodology, Recycling, Slew Rate.

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Authors: H. Daoud Dammak, S. Bensalem, S. Zouari, M. Loulou

Abstract:

This paper presents an optimized methodology to folded cascode operational transconductance amplifier (OTA) design. The design is done in different regions of operation, weak inversion, strong inversion and moderate inversion using the gm/ID methodology in order to optimize MOS transistor sizing. Using 0.35μm CMOS process, the designed folded cascode OTA achieves a DC gain of 77.5dB and a unity-gain frequency of 430MHz in strong inversion mode. In moderate inversion mode, it has a 92dB DC gain and provides a gain bandwidth product of around 69MHz. The OTA circuit has a DC gain of 75.5dB and unity-gain frequency limited to 19.14MHZ in weak inversion region.

Keywords: CMOS IC design, Folded Cascode OTA, gm/ID methodology, optimization.

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Authors: Alpana Agarwal, Akhil Sharma

Abstract:

This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for gain boosting. The Miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity-Gain Bandwidth of 107.8 MHz, and Phase Margin of 66.7^o with a power dissipation of 286 μW and makes it suitable candidate for the high resolution pipelined ADCs.

Keywords: CMOS amplifier, gain boosting, inverter-based amplifier, self-biased inverter.

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Authors: Jasdeep Kaur, Nupur Prakash, S. S. Rajput

Abstract:

A current mirror (CM) based on self cascode MOSFETs low voltage analog and mixed mode structures has been proposed. The proposed CM has high output impedance and can operate at 0.5 V. P-Spice simulations confirm the high performance of this CM with a bandwidth of 6.0 GHz at input current of 100 μA.

Keywords: Current Mirrors, Composite Cascode Structure, Current Source/Sink

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Authors: M.Yousefi, A.Vatanjou, F.Nazeri

Abstract:

A fast settling multipath CMOS OTA for high speed switched capacitor applications is presented here. With the basic topology similar to folded-cascode, bandwidth and DC gain of the OTA are enhanced by adding extra paths for signal from input to output. Designed circuit is simulated with HSPICE using level 49 parameters (BSIM 3v3) in 0.35mm standard CMOS technology. DC gain achieved is 56.7dB and Unity Gain Bandwidth (UGB) obtained is 1.15GHz. These results confirm that adding extra paths for signal can improve DC gain and UGB of folded-cascode significantly.

Keywords: OTA (Operational Transconductance Amplifier), DC gain, Unity Gain Bandwidth (UGBW)

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Authors: Salwa M. Salah Eldeen, Fathi A. Farag, Abd Allah M. Moselhy

Abstract:

This paper proposed a new CAD tools for microwave amplifier design. The proposed tool is based on survey about the broadband amplifier design methods, such as the Feedback amplifiers, balanced amplifiers and Compensated Matching Network The proposed tool is developed for broadband amplifier using a compensated matching network "unconditional stability amplifier". The developed program is based on analytical procedures with ability of smith chart explanation. The C# software is used for the proposed tools implementation. The program is applied on broadband amplifier as an example for testing. The designed amplifier is considered as a broadband amplifier at the range 300-700 MHz. The results are highly agreement with the expected results. Finally, these methods can be extended for wide band amplifier design.

Keywords: Broadband amplifier (BBA), Compensated Matching Network, Microwave Amplifier.

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Authors: Sanaz Haddadian, Rahele Hedayati

Abstract:

A 10bit, 40 MSps, sample and hold, implemented in 0.18-μm CMOS technology with 3.3V supply, is presented for application in the front-end stage of an analog-to-digital converter. Topology selection, biasing, compensation and common mode feedback are discussed. Cascode technique has been used to increase the dc gain. The proposed opamp provides 149MHz unity-gain bandwidth (wu), 80 degree phase margin and a differential peak to peak output swing more than 2.5v. The circuit has 55db Total Harmonic Distortion (THD), using the improved fully differential two stage operational amplifier of 91.7dB gain. The power dissipation of the designed sample and hold is 4.7mw. The designed system demonstrates relatively suitable response in different process, temperature and supply corners (PVT corners).

Keywords: Analog Integrated Circuit Design, Sample & Hold Amplifier and CMOS Technology.

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Authors: Renbin Dai, Rana Arslan Ali Khan

Abstract:

The design of Class A and Class AB 2-stage X band Power Amplifier is described in this report. This power amplifier is part of a transceiver used in radar for monitoring iron characteristics in a blast furnace. The circuit was designed using foundry WIN Semiconductors. The specification requires 15dB gain in the linear region, VSWR nearly 1 at input as well as at the output, an output power of 10 dBm and good stable performance in the band 10.9-12.2 GHz. The design was implemented by using inter-stage configuration, the Class A amplifier was chosen for driver stage i.e. the first amplifier focusing on the gain and the output amplifier conducted at Class AB with more emphasis on output power.

Keywords: Power amplifier, Class AB, Class A, MMIC, 2-stage, X band.

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Authors: Hafiz Muhammad Obaid, Umais Tayyab, Shabbir Majeed Ch.

Abstract:

In this paper, a CMOS differential operational transresistance amplifier (OTRA) is presented. The amplifier is designed and implemented in a standard umc90-nm CMOS technology. The differential OTRA provides wider bandwidth at high gain. It also shows much better rise and fall time and exhibits a very good input current dynamic range of 50 to 50 μA. The OTRA can be used in many analog VLSI applications. The presented amplifier has high gain bandwidth product of 617.6 THz Ω. The total power dissipation of the presented amplifier is also very low and it is 0.21 mW.

Keywords: CMOS, differential, operational transresistance amplifier, OTRA, 90 nm, VLSI.

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Authors: Kittipong Tripetch, Nobuhiko Nakano

Abstract:

Two types of floating active resistors based on a complementary regulated cascode topology with cross-coupled regulated transistors are presented in this paper. The first topology is a high swing complementary regulated cascode active resistor. The second topology is a complementary common gate with a regulated cross coupled transistor. The small-signal input resistances of the floating resistors are derived. Three graphs of the input current versus the input voltage for different aspect ratios are designed and plotted using the Cadence Spectre 0.18-µm Rohm Semiconductor process. The total harmonic distortion graphs are plotted for three different aspect ratios with different input-voltage amplitudes and different input frequencies. From the simulation results, it is observed that a resistance of approximately 8.52 MΩ can be obtained from supply voltage at  ±0.9 V.

Keywords: Complementary common gate, complementary regulated cascode, current mirror, floating active resistors.

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Authors: Jan Doutreloigne

Abstract:

The main goal of this paper is to develop a switching amplifier with optimized power efficiency for analog signals with a very high crest factor such as audio or DSL signals. Theoretical calculations show that a switching amplifier architecture based on multi-level pulse width modulation outperforms all other types of linear or switching amplifiers in that respect. Simulations on a 2 W multi-level switching audio amplifier, designed in a 50 V 0.35 mm IC technology, confirm its superior performance in terms of power efficiency. A real silicon implementation of this audio amplifier design is currently underway to provide experimental validation.

Keywords: Audio amplifier, multi-level switching amplifier, power efficiency, pulse width modulation, PWM, self-oscillating amplifier.

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Authors: Xiwei Huang, Hyouk-Kyu Cha, Dongning Zhao, Bin Guo, Minkyu Je, Hao Yu

Abstract:

This paper presents the design and implementation of a fully integrated transimpedance amplifier (TIA) as the analog frontend receiver for Capacitive Micromachined Ultrasound Transducers (CMUTs) for ultrasound biomicroscope imaging application. The amplifier is designed to amplify the received signals from 17.5MHz to 52.5MHz with a center frequency of 35MHz. The TIA was fabricated in GF 0.18μm 1P6M 30V high voltage process. The measurement results show that the designed amplifier can reach a transimpedance gain of 61.08dBΩ and operating frequency from 17.5MHz to 100MHz with 1VP-P output voltage under 6V power supply.

Keywords: 3D ultrasound biomicroscope, analog front-end, transimpedance amplifier, CMUT

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Authors: M. H. Al-Mansoori, W. S. Al-Ghaithi, F. N. Hasoon

Abstract:

In this paper, we experimentally investigate the performance of an efficient high gain triple-pass L-band Erbium-Doped Fiber (EDF) amplifier structure with a single pump source. The amplifier gain and noise figure variation with EDF pump power, input signal power and wavelengths have been investigated. The generated backward Amplified Spontaneous Emission (ASE) noise of the first amplifier stage is suppressed by using a tunable band-pass filter. The amplifier achieves a signal gain of 55 dB with low noise figure of 3.8 dB at -50 dBm input signal power. The amplifier gain shows significant improvement of 12.8 dB compared to amplifier structure without ASE suppression.

Keywords: Optical amplifiers, EDFA, L-band, optical networks.

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Authors: Jae Hyung Noh, Hang Geun Jeong

Abstract:

The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discharging current causes phase offset and reference spurs in a PLL. We propose a new charge-pump circuit to reduce the current mismatch by using a regulated cascode circuit. The proposed charge-pump circuit is designed and simulated by spectre with TSMC 0.18-μm 1.8-V CMOS technology.

Keywords: Phase-locked loop (PLL), charge-pump, phase/frequency detector (PFD), regulated cascode.

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Authors: Wang Xing-hua, Zhong Shun-an, Zhang Zhuo

Abstract:

A kind of behavior model for discrete sampling and hold amplifier with charge transmission is analyzed. The transfer function and behavior features are based on the main AC responses of operation amplifier. The result used in pipelined and sigma-delta ADC shows the exact of model of sampling and hold amplifier, and the non-ideal factors are taken into account.

Keywords: SHA, response, behavior, transfer function.

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Authors: Parekhan M. Jaff

Abstract:

This paper describes the gain and noise performances of discrete Raman amplifier as a function of fiber lengths and the signal input powers for different pump configurations. Simulation has been done by using optisystem 7.0 software simulation at signal wavelength of 1550 nm and a pump wavelength of 1450nm. The results showed that the gain is higher in bidirectional pumping than in counter pumping, the gain changes with increasing the fiber length while the noise figure remain the same for short fiber lengths and the gain saturates differently for different pumping configuration at different fiber lengths and power levels of the signal.

Keywords: Optical Amplifier, Raman Amplifier DiscreteRaman Amplifier (DRA), Wavelength Division Multiplexing(WDM).

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Authors: Makesh Iyer, T. Shanmuganantham

Abstract:

This work deals with the designing of an efficient low noise amplifier for 10.00 GHz applications. The amplifier is designed using Gallium Arsenide High Electron Mobility Transistor (GaAs HEMT) ATF – 36077 with inductive source degeneration technique which is one of the techniques to improve the stability of the potentially unstable device and make it unconditionally stable. Also, different substrates are used for designing the LNA to identify the suitable substrate that gives optimum results. It is observed that the noise immunity is more in Low Noise Amplifier (LNA) designed using RT Duroid 5880 substrate. This design resulted in noise figure of 0.859 dB and power gain of 15.530 dB. The comparative analysis of the LNA design is discussed in this paper.

Keywords: Low noise amplifier, substrate, distributed components, gain, noise figure.

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Authors: Tarun Kumar Rawat, Abhirup Lahiri, Ashish Gupta

Abstract:

In this paper, we analyze the effect of noise in a single- ended input differential amplifier working at high frequencies. Both extrinsic and intrinsic noise are analyzed using time domain method employing techniques from stochastic calculus. Stochastic differential equations are used to obtain autocorrelation functions of the output noise voltage and other solution statistics like mean and variance. The analysis leads to important design implications and suggests changes in the device parameters for improved noise characteristics of the differential amplifier.

Keywords: Single-ended input differential amplifier, Noise, stochastic differential equation, mean and variance.

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Authors: Yasir Mahmood Qureshi

Abstract:

This paper presents the design and layout of a two stage, high speed operational amplifiers using standard 0.35um CMOS technology. The design procedure involves designing the bias circuit, the differential input pair, and the gain stage using CAD tools. Both schematic and layout of the operational amplifier along with the comparison in the results of the two has been presented. The operational amplifier designed, has a gain of 93.51db at low frequencies. It has a gain bandwidth product of 55.07MHz, phase margin of 51.9º and a slew rate of 22v/us for a load of capacitor of 10pF.

Keywords: Gain bandwidth product, Operational Amplifier, phase margin, slew rate.

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Authors: Karama M. AL-Tamimi, Munir A. Al-Absi

Abstract:

A new OTA-based logarithmic-control variable gain current amplifier (LCCA) is presented. It consists of two Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The circuit operates from 0.6V DC power supply and consumes 0.6 μW. The linear-dB controllable output range is 43 dB with maximum error less than 0.5dB. The functionality of the proposed design was confirmed using HSPICE in 0.35μm CMOS process technology.

Keywords: LCCA, OTA, Logarithmic, VGA, Weak inversion, Current-mode

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Authors: Yngvar Berg, Mehdi Azadmehr

Abstract:

In this paper we present a linear autozeroing ultra lowvoltage amplifier. The autozeroing performed by all ULV circuits is important to reduce the impact of noise and especially avoid power supply noise in mixed signal low-voltage CMOS circuits. The simulated data presented is relevant for a 90nm TSMC CMOS process.

Keywords: Low-voltage, trans conductance amplifier, linearity, floating-gate.

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Authors: Chokri Jebali, Noureddine Boulejfen, Ali Gharsallah, Fadhel M. Ghannouchi

Abstract:

In this paper, a system level behavioural model for RF power amplifier, which exhibits memory effects, and based on multibranch system is proposed. When higher order terms are included, the memory polynomial model (MPM) exhibits numerical instabilities. A set of memory orthogonal polynomial model (OMPM) is introduced to alleviate the numerical instability problem associated to MPM model. A data scaling and centring algorithm was applied to improve the power amplifier modeling accuracy. Simulation results prove that the numerical instability can be greatly reduced, as well as the model precision improved with nonlinear model.

Keywords: power amplifier, orthogonal model, polynomialmodel , memory effects.

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Authors: Gianluca Cornetta, David J. Santos, Balwant Godara

Abstract:

A 1.2 V, 0.61 mA bias current, low noise amplifier (LNA) suitable for low-power applications in the 2.4 GHz band is presented. Circuit has been implemented, laid out and simulated using a UMC 130 nm RF-CMOS process. The amplifier provides a 13.3 dB power gain a noise figure NF< 2.28 dB and a 1-dB compression point of -15.69 dBm, while dissipating 0.74 mW. Such performance make this design suitable for wireless sensor networks applications such as ZigBee.

Keywords: Current Reuse, IEEE 802.15.4 (ZigBee), Low NoiseAmplifiers, Wireless Sensor Networks.

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Authors: Muhaned Zaidi, Ian Grout, Abu Khari bin A’ain

Abstract:

In this paper, a two-stage op-amp design is considered using both Miller and negative Miller compensation techniques. The first op-amp design uses Miller compensation around the second amplification stage, whilst the second op-amp design uses negative Miller compensation around the first stage and Miller compensation around the second amplification stage. The aims of this work were to compare the gain and phase margins obtained using the different compensation techniques and identify the ability to choose either compensation technique based on a particular set of design requirements. The two op-amp designs created are based on the same two-stage rail-to-rail output CMOS op-amp architecture where the first stage of the op-amp consists of differential input and cascode circuits, and the second stage is a class AB amplifier. The op-amps have been designed using a 0.35mm CMOS fabrication process.

Keywords: Op-amp, rail-to-rail output, Miller compensation, negative Miller capacitance.

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Authors: Abdalla Mohamed Eblabla

Abstract:

Due to the high increase in and demand for a wide assortment of applications that require low-cost, high-efficiency, and compact systems, RF power amplifiers are considered the most critical design blocks and power consuming components in wireless communication, TV transmission, radar, and RF heating. Therefore, much research has been carried out in order to improve the performance of power amplifiers. Classes-A, B, C, D, E and F are the main techniques for realizing power amplifiers.

An implementation of high efficiency class-F power amplifier with Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) was realized in this paper. The simulation and optimization of the class-F power amplifier circuit model was undertaken using Agilent’s Advanced Design system (ADS). The circuit was designed using lumped elements.

Keywords: Power Amplifier (PA), Gallium Nitride (GaN), Agilent’s Advanced Design system (ADS) and lumped elements.

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Authors: Maninder Kaur Gill, Alpana Agarwal

Abstract:

It is practically not feasible to measure the open-loop voltage gain of the operational amplifier in the open loop configuration. It is because the open-loop voltage gain of the operational amplifier is very large. In order to avoid the saturation of the output voltage, a very small input should be given to operational amplifier which is not possible to be measured practically by a digital multimeter. A test circuit for measurement of open loop voltage gain of an operational amplifier has been proposed and verified using simulation tools as well as by experimental methods on breadboard. The main advantage of this test circuit is that it is simple, fast, accurate, cost effective, and easy to handle even on a breadboard. The test circuit requires only the device under test (DUT) along with resistors. This circuit has been tested for measurement of open loop voltage gain for different operational amplifiers. The underlying goal is to design testable circuits for various analog devices that are simple to realize in VLSI systems, giving accurate results and without changing the characteristics of the original system. The DUTs used are LM741CN and UA741CP. For LM741CN, the simulated gain and experimentally measured gain (average) are calculated as 89.71 dB and 87.71 dB, respectively. For UA741CP, the simulated gain and experimentally measured gain (average) are calculated as 101.15 dB and 105.15 dB, respectively. These values are found to be close to the datasheet values.

Keywords: Device under test, open-loop voltage gain, operational amplifier, test circuit.

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Authors: Rahul Bansal, Sudipta Majumdar

Abstract:

This paper presents the closed form nonlinear expressions of bipolar junction transistor (BJT) differential amplifier (DA) using perturbation method. Circuit equations have been derived using Kirchhoff’s voltage law (KVL) and Kirchhoff’s current law (KCL). The perturbation method has been applied to state variables for obtaining the linear and nonlinear terms. The implementation of the proposed method is simple. The closed form nonlinear expressions provide better insights of physical systems. The derived equations can be used for signal processing applications.

Keywords: Differential amplifier, perturbation method, Taylor series.

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Authors: Haridas Kuruveettil, Dongning Zhao, Cheong Jia Hao, Minkyu Je

Abstract:

We present the design of Analog front end (AFE) low noise pre-amplifier implemented in a high voltage 0.18-µm CMOS technology for  a three dimensional ultrasound  bio microscope (3D UBM) application. The fabricated chip has 4X16 pre-amplifiers implemented to interface   a 2-D array of    high frequency capacitive micro-machined ultrasound transducers (CMUT). Core AFE cell consists of a high-voltage pulser in the transmit path, and a low-noise transimpedance amplifier in the receive path. Proposed system offers a high image resolution by the use of high frequency CMUTs with associated high performance imaging electronics integrated together.  Performance requirements and the design methods of the high bandwidth transimpedance amplifier are described in the paper. A single cell of transimpedance (TIA) amplifier and the bias circuit occupies a silicon area of 250X380 µm² and the full chip occupies a total silicon area of 10x6.8 mm².

Keywords: Ultrasound, analog front end, medical imaging, beam forming, biomicroscope, transimpedance gain.

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Authors: Arup K. George, Wai Pan Chan, Zhi Hui Kong, Minkyu Je

Abstract:

This paper describes a low-power second-order filter for a continuous-time chopper stabilized capacitive sensor interface, integrated with a fully differential post-CMOS surface-micromachined MEMS pressure sensor. The circuit uses a single-ended folded-cascode operational amplifier and two GM-C filters connected in cascade. The circuit is realized in a 0.18 μm CMOS process and offers differential to single-ended conversion. The novelty of the scheme is the cascade of two GM-C filters to achieve a second-order filter while minimizing power dissipation. The simulated filter cutoff frequency is 1.14 kHz at common-mode voltage 1.65 V, operating from a 3.3 V supply while dissipating 172μW of power. The filter achieves an operating range of 1V for an output load of 1MOhm and 10pF.

Keywords: Chopper Stabilization, MEMS, Pressure Sensors, Low Pass Filter

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Authors: Syed Iftekhar Ali, M. S. Islam

Abstract:

In this paper we present an energy efficient match-line (ML) sensing scheme for high-speed ternary content-addressable memory (TCAM). The proposed scheme isolates the sensing unit of the sense amplifier from the large and variable ML capacitance. It employs feedback in the sense amplifier to successfully detect a match while keeping the ML voltage swing low. This reduced voltage swing results in large energy saving. Simulation performed using 130nm 1.2V CMOS logic shows at least 30% total energy saving in our scheme compared to popular current race (CR) scheme for similar search speed. In terms of speed, dynamic energy, peak power consumption and transistor count our scheme also shows better performance than mismatch-dependant (MD) power allocation technique which also employs feedback in the sense amplifier. Additionally, the implementation of our scheme is simpler than CR or MD scheme because of absence of analog control voltage and programmable delay circuit as have been used in those schemes.

Keywords: content-addressable memory, energy consumption, feedback, peak power, sensing scheme, sense amplifier, ternary.

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