**Commenced**in January 2007

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**Edition:**International

**Paper Count:**30172

##### Efficient Power-Delay Product Modulo 2n+1 Adder Design

**Authors:**
Yavar Safaei Mehrabani,
Mehdi Hosseinzadeh

**Abstract:**

As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo 2n+1 adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set (2n-1,2n, 2n+1). In this manuscript we have introduced novel binary representation to the design of modulo 2n+1 adder. VLSI realization of proposed architecture under 180 nm full static CMOS technology reveals its superiority in terms of area, power consumption and power-delay product (PDP) against several peer existing structures.

**Keywords:**
Computer arithmetic,
modulo 2n+1 adders,
Residue Number System (RNS),
VLSI.

**Digital Object Identifier (DOI):**
doi.org/10.5281/zenodo.1077811

**References:**

[1] G. Lakhani, "VLSI design of modulo adders/subtractors," IEEE Int. conf. on Computer Design, ICCD'92, October 1992, PP. 68-71.

[2] W. L. Freking, and K. K. Parhi, "Low-Power FIR digital filters using residue arithmetic," proc. of 31th Asilomar Conference on Signals, Systems, and Computers, Vol. 1, November 1997, PP. 739-43.

[3] F. Taylor, "A Single Modulus ALU for Signal Processing," IEEE Trans. on Acoustics, Speech, Signal Processing, Vol. 33, 1985, PP. 1302-1315.

[4] M. Bhardwaj, and B. Ljusanin, "The Renaissance-A Residue Number System Based Vector Co-Processor for DSP Dominated Embedded ASICs," Proc. of Asimolar conference on Signals, Systems, and computers, 1998, PP. 202-207.

[5] P. G. Fernandez, A. Garcia, J. Ramirez, L. Parrilla, and A. Lioris, "A RNS-Based Matrix-Vector-Multiply FCT architecture for DCT computation," Proc. 43rd IEEE Midwest Symposium On circuits and systems, 2000, PP. 350-353.

[6] E. Kinoshita, and K. Lee, "A Residue Arithmetic Extension for Reliable Scientific Computation," IEEE Trans. on Computers, Vol. 46, No. 2, 1997, PP. 129-138.

[7] V. Paliouras, and T. Stouraitis, "Novel High-Radix Residue Number System Architectures," IEEE Trans. circuits SYST. II, Vol. 47, No. 10, October 2000, PP. 1059-1073.

[8] A. S. Molahosseini, and K. Navi, "New arithmetic Residue to Binary converters," International Journal of Computer Sciences and Engineering Systems, Vol. 1, No. 4, October 2007, PP. 295-299.

[9] B. Cao, C. H. Chang, and T. Srikanthan, "A residue-to-binary converter for a new 5-moduli set," IEEE Trans. circuits SYST. ðå, Vol. 54, No. 5, 2007, PP. 1041-1049.

[10] A. Curiger, "VLSI Architectures for computations in finite rings and fields," ph. d. thesis, Swiss federal institute of technology, 1993.

[11] R. Zimmermann, and et al., "A 177Mb/s VLSI implementation of the international data encryption algorithm," IEEE J. solid-state circuits, Vol. 29, No. 3, 1994, PP. 303-307.

[12] M. Bayoumi, and G. Jullien, "A VLSI Implementation of Residue Adders," IEEE Trans. Circuits and systems, Vol. 34, 1987, PP. 284-288.

[13] M. Dugdale, "VLSI Implementation of Residue Adders based on binary Adders," IEEE Trans. circuits SYST. II, Vol. 39, No. 5, 1992, PP. 325- 329.

[14] A. A. Hiasat, "High-speed and Reduced Area Modular Adder structures for RNS," IEEE Trans. on Computers, Vol. 51, No. 1, 2002, PP. 84-89.

[15] C. Efstathiou, and H. T. Vergos, "Fast Parallel-Prefix modulo 2n+1 Adder," IEEE Trans. on Computers, Vol. 53, No. 9, 2004, PP. 1211- 1216.

[16] G. Jaberipur, and B. Parhami, "Unified Approach to the design of Modulo-(2n┬▒1) Adders Based on Signed-LSB Representation of Residues," in proc. of the 19th IEEE Symposium on computer arithmetic, June 2009, PP. 57-64.