Search results for: Chip Micro-Hardness

Authors: Rafiqul Tarefder, Mohiuddin Ahmad, Mohammad Hossain

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While millings materials from old pavement surface can be an important component of cost effective maintenance operation, their use in maintenance projects are not uniform and well documented. This study documents the different maintenance practices followed by four transportation districts of New Mexico Department of Transportation (NMDOT) in an attempt to find whether millings are being used in maintenance projects by those districts. Based on existing literature, a questionnaire was developed related to six common maintenance practices. NMDOT district personal were interviewed face to face to discuss and get answers to that questionnaire. It revealed that NMDOT districts mainly use chip seal and patching. Other maintenance procedures such as sand seal, scrub seal, slurry seal, and thin overlay have limited use. Two out of four participating districts do not have any documents on chip sealing; rather they employ the experiences of the chip seal crew. All districts use polymer modified high float emulsion (HFE100P) for chip seal with an application rate ranging from 0.4 to 0.56 gallons per square yard. Chip application rate varies from 15 to 40 lb/ square yard. State wide, the thickness of chip seal varies from 3/8'' to 1'' and life varies from 3 to 10 years. NMDOT districts mainly use three type of patching: pothole, dig-out and blade patch. Pothole patches are used for small potholes and during emergency, dig-out patches are used for all type of potholes sometimes after pothole patching, and blade patch is used when a significant portion of the pavement is damaged. Pothole patches last as low as three days whereas, blade patch lasts as long as 3 years. It was observed that all participating districts use millings in maintenance projects.

Keywords: Chip seal, sand seal, scrub seal, slurry seal, overlay, patching, millings.

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Authors: M. Sajjadnejad, H. Omidvar, M. Javanbakht, A. Mozafari

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Pure nickel coatings have been successfully electrodeposited on copper substrates by the pulse plating technique. The influence of current density, duty cycle and pulse frequency on the surface morphology, crystal orientation, and microhardness was determined. It was found that the crystallite size of the deposit increases with increasing current density and duty cycle. The crystal orientation progressively changed from a random texture at 1 A/dm2 to (200) texture at 10 A/dm2. Increasing pulse frequency resulted in increased texture coefficient and peak intensity of (111) reflection. An increase in duty cycle resulted in considerable increase in texture coefficient and peak intensity of (311) reflection. Coatings obtained at high current densities and duty cycle present a mixed morphology of small and large grains. Maximum microhardness of 193 Hv was achieved at 4 A/dm2, 10 Hz and duty cycle of 50%. Nickel coatings with (200) texture are ductile while (111) texture improves the microhardness of the coatings.

Keywords: Current density, Duty cycle, Microstructure, Nickel, Pulse frequency.

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Authors: T. Punjansing, M. Nakkuntod, S. Homchan, P. Inthima, A. Kongbangkerd

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The influence of organic supplements on growth and multiplication efficiency of Phaius tankervilleae var. alba seedlings was investigated. 12 week-old seedlings were cultured on half-strength semi-solid Murashige and Skoog (MS) medium supplemented with 30 g/L sucrose, 8 g/L agar and various concentrations of coconut water (0, 50, 100, 150 and 200 mL/L) combined with potato extract (0, 25 and 50 g/L) and the pH was adjusted to 5.8 prior to autoclaving. The cultures were then kept under constant photoperiod (16 h light: 8 h dark) at 25 ± 2 °C for 12 weeks. The highest number of shoots (3.0 shoots/explant) was obtained when cultured on the medium added with 50 ml/L coconut water and 50 g/L potato extract whereas the highest number of leaves (5.9 leaves/explant) and roots (6.1 roots/explant) could receive on the medium supplemented with 150 ml/L coconut water and 50 g/L potato extract. with 150 ml/L coconut water and 50 g/L potato extract. Additionally, plantlets of P. tankervilleae var. alba were transferred to grow into seven different substrates i.e. soil, sand, coconut husk chip, soil-sand mix (1: 1), soil-coconut husk chip mix (1: 1), sand-coconut husk chip mix (1: 1) and soil-sand-coconut husk chip mix (1: 1: 1) for four weeks. The results found that acclimatized plants showed 100% of survivals when sand, coconut husk chip and sand-coconut husk chip mix are used as substrates. The number of leaves induced by sand-coconut husk chip mix was significantly higher than that planted in other substrates (P > 0.05). Meanwhile, no significant difference in new shoot formation among these substrates was observed (P < 0.05). This precursory developing protocol was likely to be applied for more large scale of plant production as well as conservation of germplasm of this orchid species.

Keywords: Acclimatization, coconut water, orchid, Phaius tankervilleae var. alba., potato extract.

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Authors: Guang Sun, Yong Li, Yuanyuan Zhang, Shijun Lin, Li Su, Depeng Jin, Lieguang zeng

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Network on Chip (NoC) has emerged as a promising on chip communication infrastructure. Three Dimensional Integrate Circuit (3D IC) provides small interconnection length between layers and the interconnect scalability in the third dimension, which can further improve the performance of NoC. Therefore, in this paper, a hierarchical cluster-based interconnect architecture is merged with the 3D IC. This interconnect architecture significantly reduces the number of long wires. Since this architecture only has approximately a quarter of routers in 3D mesh-based architecture, the average number of hops is smaller, which leads to lower latency and higher throughput. Moreover, smaller number of routers decreases the area overhead. Meanwhile, some dual links are inserted into the bottlenecks of communication to improve the performance of NoC. Simulation results demonstrate our theoretical analysis and show the advantages of our proposed architecture in latency, throughput and area, when compared with 3D mesh-based architecture.

Keywords: Network on Chip (NoC), interconnect architecture, performance, area, Three Dimensional Integrate Circuit (3D IC).

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Authors: A. Simoneau

Abstract:

Metal cutting is a severe plastic deformation process involving large strains, high strain rates, and high temperatures. Conventional analysis of the chip formation process is based on bulk material deformation disregarding the inhomogeneous nature of the material microstructure. A series of orthogonal cutting tests of AISI 1045 and 1144 steel were conducted which yielded similar process characteristics and chip formations. With similar shear angles and cut chip thicknesses, shear strains for both chips were found to range from 2.0 up to 2.8. The manganese-sulfide (MnS) precipitate in the 1144 steel has a very distinct and uniform shape which allows for comparison before and after chip formation. From close observations of MnS precipitates in the cut chips it is shown that the conventional approach underestimates plastic strains in metal cutting. Experimental findings revealed local shear strains around a value of 6. These findings and their implications are presented and discussed.

Keywords: Machining, metal cutting, microstructure, plastic strains, local strain.

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Authors: SreehariRao Patri, K. S. R. KrishnaPrasad

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An on chip low drop out voltage regulator that employs elegant compensation scheme is presented in this paper. The novelty in this design is that the device parasitic capacitances are exploited for compensation at different loads. The proposed LDO is designed to provide a constant voltage of 1.2V and is implemented in UMC 180 nano meter CMOS technology. The voltage regulator presented improves stability even at lighter loads and enhances line and load regulation.

Keywords: Analog, LDO, SOC.

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Authors: L.C. Kgomari, R.K.K.Mbaya

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This research was conducted to develop a correlation between microstructure of HSLA steel and the mechanical properties that occur as a result of both laser and mechanical forming processes of the metal. The technique of forming flat metals by applying laser beams is a relatively new concept in the manufacturing industry. However, the effects of laser energy on the stability of metal alloy phases have not yet been elucidated in terms of phase transformations and microhardness. In this work, CO2 laser source was used to irradiate the surface of a flat metal then the microstructure and microhardness of the metal were studied on the formed specimen. The extent to which the microstructure changed depended on the heat inputs of up to 1000 J/cm2 with cooling rates of about 4.8E+02 K/s. Experimental results revealed that the irradiated surface of a HSLA steel had transformed to austenitic structure during the heating process.

Keywords: Laser, Forming, Microstructure

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Authors: F. Majeed, D. V. Thiel, M. Shahpari

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An electrically small meander line antenna is designed for impedance matching with RF transceiver chip CC1101. The design provides the flexibility of tuning the reactance of the antenna over a wide range of values: highly capacitive to highly inductive. The antenna was printed with silver ink on FR4 substrate using the screen printing design process. The antenna impedance was perfectly matched to CC1101 at 433 MHz. The measured radiation efficiency of the antenna was 81.3% at resonance. The 3 dB and 10 dB fractional bandwidth of the antenna was 14.5% and 4.78%, respectively. The read range of the antenna was compared with a copper wire monopole antenna over a distance of five meters. The antenna, with a perfect impedance match with RF transceiver chip CC1101, shows improvement in the read range compared to a monopole antenna over the specified distance.

Keywords: Meander line antenna, RFID, Silver ink printing, Impedance matching.

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Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar

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Fast delay estimation methods, as opposed to simulation techniques, are needed for incremental performance driven layout synthesis. On-chip inductive effects are becoming predominant in deep submicron interconnects due to increasing clock speed and circuit complexity. Inductance causes noise in signal waveforms, which can adversely affect the performance of the circuit and signal integrity. Several approaches have been put forward which consider the inductance for on-chip interconnect modelling. But for even much higher frequency, of the order of few GHz, the shunt dielectric lossy component has become comparable to that of other electrical parameters for high speed VLSI design. In order to cope up with this effect, on-chip interconnect has to be modelled as distributed RLCG line. Elmore delay based methods, although efficient, cannot accurately estimate the delay for RLCG interconnect line. In this paper, an accurate analytical delay model has been derived, based on first and second moments of RLCG interconnection lines. The proposed model considers both the effect of inductance and conductance matrices. We have performed the simulation in 0.18μm technology node and an error of as low as less as 5% has been achieved with the proposed model when compared to SPICE. The importance of the conductance matrices in interconnect modelling has also been discussed and it is shown that if G is neglected for interconnect line modelling, then it will result an delay error of as high as 6% when compared to SPICE.

Keywords: Delay Modelling; On-Chip Interconnect; RLCGInterconnect; Ramp Input; Damping; VLSI

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Authors: M. Bagheri, P. Mottaghizadeh

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Reliable information about tool temperature distribution is of central importance in metal cutting. In this study, tool-chip interface temperature was determined in cutting of ST37 steel workpiece by applying HSS as the cutting tool in dry turning. Two different approaches were implemented for temperature measuring: an embedded thermocouple (RTD) in to the cutting tool and infrared (IR) camera. Comparisons are made between experimental data and results of MSC.SuperForm and FLUENT software. An investigation of heat generation in cutting tool was performed by varying cutting parameters at the stable cutting tool geometry and results were saved in a computer; then the diagrams of tool temperature vs. various cutting parameters were obtained. The experimental results reveal that the main factors of the increasing cutting temperature are cutting speed (V ), feed rate ( S ) and depth of cut ( h ), respectively. It was also determined that simultaneously change in cutting speed and feed rate has the maximum effect on increasing cutting temperature.

Keywords: Cutting parameters, Finite element modeling, Temperature measurement, Tool-chip interface temperature.

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Authors: Vedat Coskun, Fahri Soylemezgiller, Busra Ozdenizci, Kerem Ok

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In recent years, several smart card solutions for transportation services of cities with different technical infrastructures and business models has emerged considerably, which triggers new business and technical opportunities. In order to create a unique system, we present a novel, promising system called Multifunctional City Smart Card System to be used in all cities that provides transportation and loyalty services based on the MasterCard M/Chip Advance standards. The proposed system provides a unique solution for transportation services of large cities over the world, aiming to answer all transportation needs of citizens. In this paper, development of the Multifunctional City Smart Card system and system requirements are briefly described. Moreover, performance analysis results of M/Chip Advance Compatible Validators which is the system's most important component are presented.

Keywords: Smart Card, M/Chip Advance Standard, City Transportation, Performance Analysis.

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Authors: Victor E. Gromov, Evgenii A. Budovskikh, Ludmila P. Bashchenko, Yurii F. Ivanov, Anna V. Ionina, Nina A. Soskova, Guoyi Tang

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The peculiarities of the nanoscale structure-phase states formed after electroexplosive carburizing and subsequent electron-beam treatment of technically pure titanium surface in different regimes are established by methods of transmission electron diffraction microscopy and physical mechanisms are discussed. Electroexplosive carburizing leads to surface layer formation (40 m thickness) with increased (in 3.5 times) microhardness. It consists of β-titanium, graphite (monocrystals 100-150 nm, polycrystals 5-10 nm, amorphous particles 3-5nm), TiC (5-10 nm), β-Ti02 (2-20nm). After electron-beam treatment additionally increasing the microhardness the surface layer consists of TiC.

Keywords: nanoscale, phase, structure, titanium

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Authors: J. Dutta, P. Pranith Kumar Reddy

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This research paper portrays a comparative analysis of thermomechanical behaviour of Shielded Metal Arc Welding (SMAW) and Gas Tungsten Arc Welding (GTAW) of low carbon steel of AISI 1020 grade butt joints. The thermal history has been obtained by experimental work. We have focused on temperature dependent cooling rate as depicted by Adam’s two-dimensional model. The effect of moving point heat source of SMAW and GTAW on mechanical properties has been judged by optical and scanning electron micrographs of different regions in weld joints. The microhardness study has been carried to visualize the joint strength due to formation of different phases.

Keywords: Shielded metal arc welding, gas tungsten arc welding, low carbon steel, microhardness study, thermal history, microscopic morphology.

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Authors: Ching-Feng Chen, Ching-Chih Tsai

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With the size of the transistor gradually approaching the physical limit, it challenges the persistence of Moore’s Law due to such issues of the short channel effect and the development of the high numerical aperture (NA) lithography equipment. In the context of the ever-increasing technical requirements of portable devices and high-performance computing (HPC), relying on the law continuation to enhance the chip density will no longer support the prospects of the electronics industry. Weighing the chip’s power consumption-performance-area-cost-cycle time to market (PPACC) is an updated benchmark to drive the evolution of the advanced wafer nanometer (nm). The advent of two and half- and three-dimensional (2.5 and 3D)- Very-Large-Scale Integration (VLSI) packaging based on Through Silicon Via (TSV) technology has updated the traditional die assembly methods and provided the solution. This overview investigates the up-to-date and cutting-edge packaging technologies for 2.5D and 3D integrated circuits (IC) based on the updated transistor structure and technology nodes. We conclude that multi-chip solutions for 2.5D and 3D IC packaging can prolong Moore’s Law.

Keywords: Moore’s Law, High Numerical Aperture, Power Consumption-Performance-Area-Cost-Cycle Time to Market, PPACC, 2.5 and 3D-Very-Large-Scale Integration Packaging, Through Silicon Vi.

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Authors: M. S. Kaiser, S. Reaz Ahmed

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Chip formation characteristics are investigated during surface finishing of high density polyethylene (HDPE) samples using a shaper machine. Both the cutting speed and depth of cut are varied continually to enable observations under various machining conditions. The generated chips are analyzed in terms of their shape, size, and deformation. Their physical appearances are also observed using digital camera and optical microscope. The investigation shows that continuous chips are obtained for all the cutting conditions. It is observed that cutting speed is more influential than depth of cut to cause dimensional changes of chips. Chips curl radius is also found to increase gradually with the increase of cutting speed. The length of continuous chips remains always smaller than the job length, and the corresponding discrepancies are found to be more prominent at lower cutting speed. Microstructures of the chips reveal that cracks are formed at higher cutting speeds and depth of cuts, which is not that significant at low depth of cut.

Keywords: HDPE, surface-finishing, chip formation, deformation, roughness.

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Authors: Faizal A. Samman, Thomas Hollstein, Manfred Glesner

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This paper presents design trade-off and performance impacts of the amount of pipeline phase of control path signals in a wormhole-switched network-on-chip (NoC). The numbers of the pipeline phase of the control path vary between two- and one-cycle pipeline phase. The control paths consist of the routing request paths for output selection and the arbitration paths for input selection. Data communications between on-chip routers are implemented synchronously and for quality of service, the inter-router data transports are controlled by using a link-level congestion control to avoid lose of data because of an overflow. The trade-off between the area (logic cell area) and the performance (bandwidth gain) of two proposed NoC router microarchitectures are presented in this paper. The performance evaluation is made by using a traffic scenario with different number of workloads under 2D mesh NoC topology using a static routing algorithm. By using a 130-nm CMOS standard-cell technology, our NoC routers can be clocked at 1 GHz, resulting in a high speed network link and high router bandwidth capacity of about 320 Gbit/s. Based on our experiments, the amount of control path pipeline stages gives more significant impact on the NoC performance than the impact on the logic area of the NoC router.

Keywords: Network-on-Chip, Synchronous Parallel Pipeline, Router Architecture, Wormhole Switching

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Authors: Md. Anayet U. Patwari, Mohammad Ahsan Habib, Md. Tanzib Ehsan, Md Golam Ahnaf, Md. S. I. Chowdhury

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Surface roughness is one of the key quality parameters of the finished product. During any machining operation, high temperatures are generated at the tool-chip interface impairing surface quality and dimensional accuracy of products. Cutting fluids are generally applied during machining to reduce temperature at the tool-chip interface. However, usages of cutting fluids give rise to problems such as waste disposal, pollution, high cost, and human health hazard. Researchers, now-a-days, are opting towards dry machining and other cooling techniques to minimize use of coolants during machining while keeping surface roughness of products within desirable limits. In this paper, a concept of using peltier cooling effects during aluminium milling operation has been presented and adopted with an aim to improve surface roughness of the machined surface. Experimental evidence shows that peltier cooling effect provides better surface roughness of the machined surface compared to dry machining.

Keywords: Aluminium, surface roughness, Peltier cooling effect, milling operation.

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Authors: Sanjay Kumar Awasthi, Sunil Kumar Bajpai, Surendra Kumar Pandey, Ajay Utiye

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The effect of gamma irradiation on micro-hardness of polymer blends of poly (ethyl methacrylate)(PEMA) and poly (ethylene oxide) (PEO) has been investigated to detect the radiation induced crosslinking. The blend system comprises a noncrystallizable polymer, PEMA and a crystallizable polymer, PEO. On irradiation, the overall hardness of the blend specimens for different dose levels infers occurrence of a crosslinking process. The radiation-induced crosslinking was greater for blends having lower concentration of PEO. However, increase in radiation dose causes softening of blend system due to radiation induced scissioning of the chains

Keywords: Microhardness, Radiation induced crosslinking, Solution cast technique, Vicker's hardness number.

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Authors: Zainudin Kornain, Azman Jalar, Rozaidi Rasid, Fong Chee Seng

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Void formation in underfill is considered as failure in flip chip manufacturing process. Void formation possibly caused by several factors such as poor soldering and flux residue during die attach process, void entrapment due moisture contamination, dispense pattern process and setting up the curing process. This paper presents the comparison of single step and two steps curing profile towards the void and black dots formation in underfill for Hi-CTE Flip Chip Ceramic Ball Grid Array Package (FC-CBGA). Statistic analysis was conducted to analyze how different factors such as wafer lot, sawing technique, underfill fillet height and curing profile recipe were affected the formation of voids and black dots. A C-Mode Scanning Aqoustic Microscopy (C-SAM) was used to scan the total count of voids and black dots. It was shown that the 2 steps curing profile provided solution for void elimination and black dots in underfill after curing process.

Keywords: black dots formation, curing profile, FC-CBGA, underfill, void formation,

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Authors: M. K. Benhaoua, A. K. Singh, A. E. H. Benyamina, A. Kumar, P. Boulet

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In this paper, we propose a new packing strategy to find a free resource for run-time mapping of application tasks to NoC-based Heterogeneous MPSoC. The proposed strategy minimizes the task mapping time in addition to placing the communicating tasks close to each other. To evaluate our approach, a comparative study is carried out for a platform containing single task supported PEs. Experiments show that our strategy provides better results when compared to latest dynamic mapping strategies reported in the literature.

Keywords: Multi-Processor Systems-on-Chip (MPSoCs), Network-on-Chip (NoC), Heterogeneous architectures, Dynamic mapping heuristics.

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Authors: Petr Homola, Lucie Novakova, Vaclav Kafka, Mariluz P. Oscoz

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Shear spinning is closely related to the asymmetric incremental sheet forming (AISF) that could significantly reduce costs incurred by the fabrication of complex aeronautical components with a minimal environmental impact. The spinning experiments were carried out on commercially pure titanium (Ti-Gr2) and Ti-6Al-4V (Ti-Gr5) alloy. Three forming modes were used to characterize the titanium alloys properties from the point of view of different spinning parameters. The structure and properties of the materials were assessed by means of metallographic analyses and microhardness measurements. The highest value wall angle failure limit was achieved using spinning parameters mode for both materials. The feed rate effect was observed only in the samples from the Ti-Gr2 material, when a refinement of the grain microstructure with lower feed rate and higher tangential speed occurred. Ti-Gr5 alloy exhibited a decrease of the microhardness at higher straining due to recovery processes.

Keywords: Incremental forming, metallography, shear spinning, titanium alloys.

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Authors: I. Kurashvili, A. Sichinava, G. Bokuchava, G. Darsavelidze

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Si-Ge solid solutions (bulk poly- and mono-crystalline samples, thin films) are characterized by high perspectives for application in semiconductor devices, in particular, optoelectronics and microelectronics. From this point of view, complex studying of structural state of the defects and structural-sensitive physical properties of Si-Ge solid solutions depending on the contents of Si and Ge components is very important. Present work deals with the investigations of microstructure, microhardness, internal friction and shear modulus of Si1-xGex(x≤0,02) bulk monocrystals conducted at room temperature. Si-Ge bulk crystals were obtained by Czochralski method in [111] crystallographic direction. Investigated monocrystalline Si-Ge samples are characterized by p-type conductivity and carriers’ concentration 5.1014-1.1015cm-3. Microhardness was studied on Dynamic Ultra Micro hardness Tester DUH-201S with Berkovich indenter. Investigate samples are characterized with 0,5x0,5x(10-15)mm3 sizes, oriented along [111] direction at torsion oscillations ≈1Hz, multistage changing of internal friction and shear modulus has been revealed in an interval of strain amplitude of 10-5-5.10-3. Critical values of strain amplitude have been determined at which hysteretic changes of inelastic characteristics and microplasticity are observed. The critical strain amplitude and elasticity limit values are also determined. Dynamic mechanical characteristics decreasing trend is shown with increasing Ge content in Si-Ge solid solutions. Observed changes are discussed from the point of view of interaction of various dislocations with point defects and their complexes in a real structure of Si-Ge solid solutions.

Keywords: Internal friction, microhardness, relaxation processes, shear modulus, Si-Ge.

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Authors: Y. Ni, K. Sebri

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The practical implementation of audio-video coupled speech recognition systems is mainly limited by the hardware complexity to integrate two radically different information capturing devices with good temporal synchronisation. In this paper, we propose a solution based on a smart CMOS image sensor in order to simplify the hardware integration difficulties. By using on-chip image processing, this smart sensor can calculate in real time the X/Y projections of the captured image. This on-chip projection reduces considerably the volume of the output data. This data-volume reduction permits a transmission of the condensed visual information via the same audio channel by using a stereophonic input available on most of the standard computation devices such as PC, PDA and mobile phones. A prototype called VMIKE (Visio-Microphone) has been designed and realised by using standard 0.35um CMOS technology. A preliminary experiment gives encouraged results. Its efficiency will be further investigated in a large variety of applications such as biometrics, speech recognition in noisy environments, and vocal control for military or disabled persons, etc.

Keywords: Audio-Visual Speech recognition, CMOS Smartsensor, On-Chip image processing.

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Authors: Lucie Novakova, Petr Homola, Vaclav Kafka

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Asymmetric incremental sheet forming (AISF) could significantly reduce costs incurred by the fabrication of complex industrial components with a minimal environmental impact. The AISF experiments were carried out on commercially pure titanium (Ti-Gr2), Timetal (15-3-3-3) alloy, and Ti-6Al-4V (Ti-Gr5) alloy. A special testing geometry was used to characterize the titanium alloys properties from the point of view of the forming zone and titanium structure effect. The structure and properties of the materials were assessed by means of metallographic analyses and microhardness measurements.The highest differences in the parameters assessed as a function of the sampling zone were observed in the case of alpha-phase Ti-Gr2at the expense of the most substantial sheet thinning occurrence. A springback causes a smaller stored deformation in Timetal (β alloy) resulting in less pronounced microstructure refinement and microhardness increase. Ti-6Al-4V alloy exhibited early failure due to its poor formability at ambient temperature.

 

Keywords: Incremental forming, metallography, hardness, titanium alloys.

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Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar

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This work proposes an accurate crosstalk noise estimation method in the presence of multiple RLC lines for the use in design automation tools. This method correctly models the loading effects of non switching aggressors and aggressor tree branches using resistive shielding effect and realistic exponential input waveforms. Noise peak and width expressions have been derived. The results obtained are at good agreement with SPICE results. Results show that average error for noise peak is 4.7% and for the width is 6.15% while allowing a very fast analysis.

Keywords: Crosstalk, distributed RLC segments, On-Chip interconnect, output response, VLSI, noise peak, noise width.

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Authors: Shiyang Zhu, G. Q. Lo, D. L. Kwong

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Silicon photonics is merging as a unified platform for driving photonic based telecommunications and for local photonic based interconnect but it suffers from large footprint as compared with the nanoelectronics. Plasmonics is an attractive alternative for nanophotonics. In this work, two CMOS compatible plasmonic waveguide platforms are compared. One is the horizontal metal-insulator-Si-insulator-metal nanoplasmonic waveguide and the other is metal-insulator-Si hybrid plasmonic waveguide. Various passive and active photonic devices have been experimentally demonstrated based on these two plasmonic waveguide platforms.

Keywords: Plasmonics, on-chip integration, Silicon photonics.

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Authors: Yuanyuan Zhang, Guang Sun, Li Su, Depeng Jin, Lieguang Zeng

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Since Network-on-Chip (NoC) uses network interfaces (NIs) to improve the design productivity, by now, there have been a few papers addressing the design and implementation of a NI module. However, none of them considered the difference of address encoding methods between NoC and the traditional bus-shared architecture. On the basis of this difference, in the paper, we introduce a transmit mechanism to solve such a problem for global asynchronous locally synchronous (GALS) NoC. Furthermore, we give the concrete implementation of the NI module in this transmit mechanism. Finally, we evaluate its performance and area overhead by a VHDL-based cycle-accurate RTL model and simulation results confirm the validity of this address-oriented transmit mechanism.

Keywords: Network-on-Chip, Network Interface, Open CoreProtocol, Address.

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Authors: Panagiotis Kyratsis, Dr. Ing. Nikolaos Bilalis, Dr. Ing. Aristomenis Antoniadis

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Twist drills are geometrical complex tools and thus various researchers have adopted different mathematical and experimental approaches for their simulation. The present paper acknowledges the increasing use of modern CAD systems and using the API (Application Programming Interface) of a CAD system, drilling simulations are carried out. The developed DRILL3D software routine, creates parametrically controlled tool geometries and using different cutting conditions, achieves the generation of solid models for all the relevant data involved (drilling tool, cut workpiece, undeformed chip). The final data derived, consist a platform for further direct simulations regarding the determination of cutting forces, tool wear, drilling optimizations etc.

Keywords: Drilling, CAD based simulation, 3D-modelling.

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Authors: Stephen Akinlabi, Mukul Shukla, Esther Akinlabi, Marwala Tshilidzi

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This paper reports the evolving properties of a 3 mm low carbon steel plate after Laser Beam Forming achieve this objective, the chemical analyse material and the formed components were carried thereafter both were characterized through microhardness profiling microstructural evaluation and tensile testing. showed an increase in the elemental concentration of the component when compared to the as received attributed to the enhancement property of the LBF process Ultimate Tensile Strength (UTS) and the Vickers the formed component shows an increase when compared to the as received material, this was attributed to strain hardening and grain refinement brought about by the LBF process. The microstructure of the as received steel consists of equiaxed ferrit that of the formed component exhibits elongated orming process (LBF). To es of the as received out and compared; profiling, The chemical analyses formed material; this can be process. The microhardness of ferrite and pearlite while grains.

Keywords: Laser beam forming, deformation , deformation, elongated grains

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Authors: Nawang Chhunid, Gagnesh Kumar

Abstract:

On-chip memories consume a significant portion of the overall die space and power in modern microprocessors. On-chip caches depend on Static Random-Access Memory (SRAM) cells and scaling of technology occurring as per Moore’s law. Unfortunately, the scaling is affecting stability, performance, and leakage power which will become major problems for future SRAMs in aggressive nanoscale technologies due to increasing device mismatch and variations. 3T1D Dynamic Random-Access Memory (DRAM) cell is a non-destructive read DRAM cell with three transistors and a gated diode. In 3T1D DRAM cell gated diode (D1) acts as a storage device and also as an amplifier, which leads to fast read access. Due to its high tolerance to process variation, high density, and low cost of memory as compared to 6T SRAM cell, it is universally used by the advanced microprocessor for on chip data and program memory. In the present paper, it has been shown that 3T1D DRAM cell can perform better in terms of fast read access as compared to 6T, 4T, 3T SRAM cells, respectively.

Keywords: DRAM cell, read access time, tanner EDA tool write access time and retention time, average power dissipation.

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