Pipelined Control-Path Effects on Area and Performance of a Wormhole-Switched Network-on-Chip

Authors: Faizal A. Samman, Thomas Hollstein, Manfred Glesner

Abstract:

This paper presents design trade-off and performance impacts of the amount of pipeline phase of control path signals in a wormhole-switched network-on-chip (NoC). The numbers of the pipeline phase of the control path vary between two- and one-cycle pipeline phase. The control paths consist of the routing request paths for output selection and the arbitration paths for input selection. Data communications between on-chip routers are implemented synchronously and for quality of service, the inter-router data transports are controlled by using a link-level congestion control to avoid lose of data because of an overflow. The trade-off between the area (logic cell area) and the performance (bandwidth gain) of two proposed NoC router microarchitectures are presented in this paper. The performance evaluation is made by using a traffic scenario with different number of workloads under 2D mesh NoC topology using a static routing algorithm. By using a 130-nm CMOS standard-cell technology, our NoC routers can be clocked at 1 GHz, resulting in a high speed network link and high router bandwidth capacity of about 320 Gbit/s. Based on our experiments, the amount of control path pipeline stages gives more significant impact on the NoC performance than the impact on the logic area of the NoC router.

Keywords: Network-on-Chip, Synchronous Parallel Pipeline, Router Architecture, Wormhole Switching

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1073557

References:

[1] P. Martin, "Design of a Virtual Component Neutral Network-on- Chip Transaction Layer," Proc. Design, Automation and Test in Europe Conf. and Exhibition (DATE-05), pp. 336-337, 2005.
[2] D. Wingard, "MicroNetwork-Based Integration for SOCs," Proc. Design Automation Conf. (DAC-01), pp. 673-677, 2001.
[3] L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm," IEEE Computer, vol. 35, pp. 70-78, Jan. 2002.
[4] A. Jantsch and H. Tenhunen, Networks on Chip, Kluwer Academic Publisher, Hingham, MA, USA, 2003.
[5] M. Millberg, E. Nilsson, R. Thid and A. Jantsch, "Guaranteed Bandwidth using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip," Proc. Design, Automation and Test in Europe Conf. and Exhibition (DATE-04), pp. 890-895, 2004.
[6] D. Wiklund and D. Liu, "SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems," Proc. IEEE Int-l Parallel and Distributed Processing Symposium (IPDPS-03), 8 pp., 2003.
[7] M. B. Taylor, J. Kim, J. Miller, D. Wentzlaff, F. Ghodrat, B. Greenwald, H. Hoffman, et. al., "The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs," IEEE Micro, vol. 22, issue 2, pp. 25-35, Mar-Apr. 2002.
[8] C. Hilton and B. Nelson, "PNOC: a flexible circuit-switched NoC for FPGA-based systems," IEE Proc. Computers and Digital Techniques, vol. 153, no.3, pp. 181-188, May 2006.
[9] S. Kumar, A. Jantsch, J. -K. Soininen, M. Forsell, M. Millberg, J. O¨ berg, K. Tiensyrja and A. Hemani, "A Network on Chip Architecture and Design Methodology," Proc. IEEE Computer Society Annual Symposium on VLSI, pp. 105-112, 2002.
[10] M. K. -F. Sch¨afer, T. Hollstein, H. Zimmer, M. Glesner, "Deadlock- Free Routing and Component Placement for Irregular Mesh-based Network-on-Chip," IEEE/ACM Int-l Conf. on CAD (ICCAD-05), pp. 238-245, 2005.
[11] F. Karim, A. Nguyen and S. Dey, "An Interconnect Architecture for Networking Systems on Chips," IEEE Micro, vol. 22, issue 5, pp. 36-45, Sept-Oct. 2002.
[12] P. Guerrier and A. Greiner, "A Generic Architecture for On-Chip Packet-Switched Interconnection," Proc. Design, Automation and Test in Europe Conf. and Exhibition (DATE-00), pp. 250-256, 2000.
[13] I. M. Panades, A. Greiner and A. Sheibanyrad, "A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach," Proc. the 1st Int-l Conf. and Workshop on Nano- Networks), pp. 1-5, 2006.
[14] E. Rijpkema, K. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage and E. Waterlander, "Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip," IEE Proc. Computers and Digital Techniques, vol. 150, no. 5, pp. 294-302, Sep. 2003.
[15] T. A. Bartic, J. -Y. Mignolet, V. Nollet, T. Marescaux, D. Verkest, S. Vernalde and R. Lauwereins, "Topology adaptive network-onchip design and implementation," IEE Proc. Computers and Digital Techniques, vol. 152, no.4, pp. 467-472, July 2005.
[16] L. Benini and D. Bertozzi, "Network-on-chip architectures and design methods," IEE Proc. Computers and Digital Techniques, vol. 152, no.2, pp. 261-272, Mar. 2005.
[17] J. Xu, W. Wolf, J. Henkel and S. Chakradhar, "A Design Methodology for application-Specific Networks-on-Chip," ACM Trans. on Embedded Computing Systems, vol. 5, no. 2, pp. 263-280, May 2006.
[18] J. Bainbridge and S. Furber, "Chain: A Delay-Insensitive Chip Area Interconnect," IEEE Micro, vol. 22, issue 5, pp. 16-23, Sept-Oct. 2002.
[19] M. Amde, T. Felicijan, A. Efthymiou, D. Edwards and L. Lavagno, "Asynchronous on-chip networks," IEE Proc. Computers and Digital Techniques, vol. 152, no. 2, pp. 273-283, Mar. 2005.
[20] M. Sgroi, M. Sheets, K. Keutzer, S. Malik, J. Rabaey and A. S. Vincentelli, "Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design," The 38th ACM Design Automation Conf. (DAC-01), pp. 667-672, 2001.
[21] I. Saastamoinen, D. S. -Tortosa and J. Nurmi, "Interconnect IP Node for Future System-on-Chip Designs," The 1st IEEE Int-l Workshop on Electronic Design, Test and Applications (DELTA-02), pp. 116- 120, 2002.
[22] E. Beign'e, F. Clermidy, P. Vivet, A. Clouard and M. Renaudin, "An Asynchronous NOC Architecture Providing Low Latency Service and its Muti-level Design Framework," Proc. the 11th IEEE Int-l Symp. on Asynchronous Circuits and Systems, pp. 54-63, 2005.
[23] T. Bjerregaard and J. Spars├©, "Implementation of guaranteed services in the MANGO clockless network-on-chip," IEE Proc. Computers and Digital Techniques, vol. 153, no.4, pp. 217-229, July 2006.
[24] J. Kim, D. Park, N. Vijaykrishnan and C. R. Das, "A Low Latency Router Supporting Adaptivity for On-Chip Interconnects, " ACM Design Automation Conf. (DAC-05), pp. 559-564, 2005.