Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 32313
Effect of Curing Profile to Eliminate the Voids / Black Dots Formation in Underfill Epoxy for Hi-CTE Flip Chip Packaging

Authors: Zainudin Kornain, Azman Jalar, Rozaidi Rasid, Fong Chee Seng


Void formation in underfill is considered as failure in flip chip manufacturing process. Void formation possibly caused by several factors such as poor soldering and flux residue during die attach process, void entrapment due moisture contamination, dispense pattern process and setting up the curing process. This paper presents the comparison of single step and two steps curing profile towards the void and black dots formation in underfill for Hi-CTE Flip Chip Ceramic Ball Grid Array Package (FC-CBGA). Statistic analysis was conducted to analyze how different factors such as wafer lot, sawing technique, underfill fillet height and curing profile recipe were affected the formation of voids and black dots. A C-Mode Scanning Aqoustic Microscopy (C-SAM) was used to scan the total count of voids and black dots. It was shown that the 2 steps curing profile provided solution for void elimination and black dots in underfill after curing process.

Keywords: black dots formation, curing profile, FC-CBGA, underfill, void formation,

Digital Object Identifier (DOI):

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3945


[1] K. Kotaka, O. Suzuki and Y. Homma, " The Latest Underfill Materials for Flipchip Applications" in Proc. 4th International Symposium in Material Packaging , 2002, pp. 43-48
[2] M. Ying, A. Tengh, Y. C. Chea, and A. Mohtar, "Pb-free Solder Bump Reliability Evaluation for Flip-Chip-on Board", in Proc. SEMI Technology Symposium, Singapore, 2006, pp. 46-52
[3] T. Wang, J. M. Ling, M. Ying, et al, "The Effect of Underfill Materials on Lead-free Flip Chip Package Reliability", Topical Workshop and Exhibition on Flip Chip Technology, IMAPS, USA, 2004. pp. 57-62
[4] S. B. Park, S. W. Chung and Z. Tang, "Experimental Evidence of Underfill Voiding and Delamination during Board Level Assembly of Pb-free Solders", in Proc. 11th International Symposium on Advance Packaging Material, Processes, Properties and Interface, Atlanta, 2006, pp. 43-50
[5] S. Lee; M. J. Yim, R. N. Master, C. P. Wong, D. F. Baldwin, "Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill", IEEE Trans. Electronics Packaging Manufacturing, vol. 32, 2009, pp. 106-114
[6] M. Ying, A. Tengh, Y.C. Chea, "Process Development of Void Free Underfilling for Flip-chip-on-board", in Proc. 9th IEEE Electronics Packaging Technology Conference, Singapore, 2007, pp. 805-810
[7] M. Colella, and D. Baldwin, "Near void-free no-flow underfill flip chip on board assembly technology reliability characterization", in Proc. International Manufacturing Technology Symposium, USA, 2004, pp. 223-228
[8] S. L. B. Dal and N. T. Zamora "Identification of new mechanism of epoxy underfill void formation in electronic packages", in Proc. IEEE Reliability Physics Symposium, Philippines, 2005, pp. 508-512
[9] E. Goh, X. L. Zhao, Ashok Anand, and Y. C. Mui, "Mechanism of Underfill Voids Formation in Flip Chip Packaging", in Proc. 7th IEEE Electronics Packaging Technology Conference, Singapore ,2005, pp. 101-107
[10] P. S. Ho, Z.P. Xiong, K.H. Chua, "Study on Factors Affecting Underfill Flow and Underfill Voids in a Large-die Flip Chip Ball GridArray (FCBGA) Package", in Proc. 9th IEEE Electronics Packaging Technology Conference, Singapore 2007, pp 640-645