Search results for: Reduction power

Authors: M. Yousefi, N. Nasirzadeh

Abstract:

In this paper, dynamic comparator structure employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters have been presented. The proposed comparator has low consumption thanks to power reduction methods. They have the ability for offset adjustment. The comparator consumes 14.3 μW at 100 MHz which is equal to 11.8 fJ. The comparator has been designed and simulated in 180 nm CMOS. Layouts occupy 210 μm².

Keywords: Comparator, low, power, efficiency.

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Authors: Pardeep Singh, Sanjay Sharma, Parvinder S. Sandhu

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This work aims to reduce the read power consumption as well as to enhance the stability of the SRAM cell during the read operation. A new 10-transisor cell is proposed with a new read scheme to minimize the power consumption within the memory core. It has separate read and write ports, thus cell read stability is significantly improved. A 16Kb SRAM macro operating at 1V supply voltage is demonstrated in 65 nm CMOS process. Its read power consumption is reduced to 24% of the conventional design. The new cell also has lower leakage current due to its special bit-line pre-charge scheme. As a result, it is suitable for low-power mobile applications where power supply is restricted by the battery.

Keywords: A 16Kb 10T-SRAM, 4x Read-Power Reduction

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Authors: Sanjay Singh, M Sathish Kumar, H. S Mruthyunjaya

Abstract:

Multicarrier transmission system such as Orthogonal Frequency Division Multiplexing (OFDM) is a promising technique for high bit rate transmission in wireless communication system. OFDM is a spectrally efficient modulation technique that can achieve high speed data transmission over multipath fading channels without the need for powerful equalization techniques. However the price paid for this high spectral efficiency and less intensive equalization is low power efficiency. OFDM signals are very sensitive to nonlinear effects due to the high Peak-to-Average Power Ratio (PAPR), which leads to the power inefficiency in the RF section of the transmitter. This paper investigates the effect of PAPR reduction on the performance parameter of multicarrier communication system. Performance parameters considered are power consumption of Power Amplifier (PA) and Digital-to-Analog Converter (DAC), power amplifier efficiency, SNR of DAC and BER performance of the system. From our analysis it is found that irrespective of PAPR reduction technique being employed, the power consumption of PA and DAC reduces and power amplifier efficiency increases due to reduction in PAPR. Moreover, it has been shown that for a given BER performance the requirement of Input-Backoff (IBO) reduces with reduction in PAPR.

Keywords: BER, Crest Factor (CF), Digital-to-Analog Converter(DAC), Input-Backoff (IBO), Orthogonal Frequency Division Multiplexing(OFDM), Peak-to-Average Power Ratio (PAPR), PowerAmplifier efficiency, SNR

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Authors: P.K. Sharma, B. Bhargava, S. Akashe

Abstract:

Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.

Keywords: Stack, 6T SRAM cell, low power, threshold voltage

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Authors: Priyanka Sen, Kaibalya Prasad Panda, Soumyakanta Samantaray, Sreyasee Rout, Bishnupriya Biswal

Abstract:

Deregulation in the power system industry and the invention of new technologies for producing electrical energy has led to innovations in power system planning. Distributed generation (DG) is one of the most attractive technologies that bring different kinds of advantages to a lot of entities, engaged in power systems. In this paper, a model for considering DGs in the power system planning problem is presented. Dynamic power system planning for reduction of maintenance and operational cost is presented in this paper. In addition to that, a modified particle swarm optimization (PSO) is used to find the optimal topology solution. Voltage Profile Improvement Index (VPII) and Line Loss Reduction Index (LLRI) are taken as benefit index of employing DG. The effectiveness of this method is demonstrated through examination of IEEE 30 bus test system.

Keywords: Distributed generation, line loss reduction index, particle swarm optimization, power system, voltage profile improvement index.

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Authors: C. Iraklis, G. Evmiridis, A. Iraklis

Abstract:

Renewable energy sources and distributed power generation units already have an important role in electrical power generation. A mixture of different technologies penetrating the electrical grid, adds complexity in the management of distribution networks. High penetration of distributed power generation units creates node over-voltages, huge power losses, unreliable power management, reverse power flow and congestion. This paper presents an optimization algorithm capable of reducing congestion and power losses, both described as a function of weighted sum. Two factors that describe congestion are being proposed. An upgraded selective particle swarm optimization algorithm (SPSO) is used as a solution tool focusing on the technique of network reconfiguration. The upgraded SPSO algorithm is achieved with the addition of a heuristic algorithm specializing in reduction of power losses, with several scenarios being tested. Results show significant improvement in minimization of losses and congestion while achieving very small calculation times.

Keywords: Congestion, distribution networks, loss reduction, particle swarm optimization, smart grid.

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Authors: Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj

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Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.

Keywords: Deep submicron, Leakage Current, LECTOR, ONOFIC, Power Delay Product

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Authors: M. Mohamadi, A. M. Maskooki., S. A. Mortazavi

Abstract:

The quality and shelf life of foods of containing lipids (fats and oils) significantly reduces due to rancidity.Applications of natural antioxidants are one of the most effective manners to prevent the oxidation of oils and lipids. The antioxidant properties of juice extracted from barberry fruit (Berberris vulgaris.L) using maceration and SWE (10 bars and 120 - 180°C) methods were investigated and compared with conventional method. The amount of phenolic compound and reduction power of all samples were determined and the data were statistically analyzed using multifactor design. The results showed that the total amount of phenolic compound increased with increasing of pressure and temprature from 1861.9 to 2439.1 (mg Gallic acid /100gr Dry matter). The ability of reduction power of SWE obtained antioxidant extract compared with BHA (synthetic antioxidant) and ascorbic acid (natural antioxidant). There were significant differences among reduction power of extracts and there were remarkable difference with BHA and Ascorbic acid (P<0.01).

Keywords: Subcritical water, Antioxidant, Barberry, Phenolic compound, Reduction power

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Authors: Md. Mahmudul Hasan

Abstract:

OFDM systems are known to have a high PAPR (Peak-to-Average Power Ratio) compared with single-carrier systems. In fact, the high PAPR is one of the most detrimental aspects in the OFDM system, as it can cause power degradation (Inband distortion) and spectral spreading (Out-of-band radiation). In this paper, from the foundation of the PAPR analysis an effective method of PAPR reduction has been proposed based on Orthogonal Eigenvector Matrix (OEM) transform. Extensive computer simulations show that a PAPR reduction of up to 4.4 dB can be obtained without introducing in-band distortion or out-of-band radiation in the system.

Keywords: Orthogonal frequency division multiplexing (OFDM), peak-to-average power ratio (PAPR), Orthogonal Eigenvector Matrix (OEM).

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Authors: Wisam F. Al-Azzo, Borhanuddin Mohd. Ali

Abstract:

This paper addresses the problem of peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing (OFDM) systems. It also introduces a new PAPR reduction technique based on adaptive square-rooting (SQRT) companding process. The SQRT process of the proposed technique changes the statistical characteristics of the OFDM output signals from Rayleigh distribution to Gaussian-like distribution. This change in statistical distribution results changes of both the peak and average power values of OFDM signals, and consequently reduces significantly the PAPR. For the 64QAM OFDM system using 512 subcarriers, up to 6 dB reduction in PAPR was achieved by square-rooting technique with fixed degradation in bit error rate (BER) equal to 3 dB. However, the PAPR is reduced at the expense of only -15 dB out-ofband spectral shoulder re-growth below the in-band signal level. The proposed adaptive SQRT technique is superior in terms of BER performance than the original, non-adaptive, square-rooting technique when the required reduction in PAPR is no more than 5 dB. Also, it provides fixed amount of PAPR reduction in which it is not available in the original SQRT technique.

Keywords: complementary cumulative distribution function(CCDF), OFDM, peak-to-average power ratio (PAPR), adaptivesquare-rooting PAPR reduction technique.

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Authors: Gomaa N. Abdel-Rahman, Nadia R. A. Nassar, Yehia A. Heikal, Mahmoud A. M. Abou-Donia, Mohamed B. M. Ahmed, Mohamed Fadel

Abstract:

Storage stability is the important factor of baker's yeast quality. Effect of the storage period (fifteen days) on storage sugars and cell viability of baker's yeast, produced from three S. cerevisiae strains (FC-620, FH-620, and FAT-12) as comparison with baker's yeast produced by S. cerevisae F-707 (original strain of baker's yeast factory) were investigated. Studied trehalose and glycogen content ranged from 10.19 to 14.79 % and from 10.05 to 10.69 % (d.w.), respectively before storage. The trehalose and glycogen content of all strains was decreased by increasing the storage period with no significant differences between the reduction rates of trehalose. Meanwhile, reduction rates of glycogen had significant differences between different strains, where the FH-620 and FC-620 strains had lowest rates as 18.12 and 20.70 %, respectively. Also, total viable cells and gassing power of all strains were decreased by increasing the storage period. FH-620 and FC-620 strains had the lowest values of reduction rates as an indicator of storage resistant. Where the reduction rates in total viable cells of FH-620 and FC-620 strains were 22.05 and 24.70%, respectively, while the reduction rates of gassing power were 20.90 and 24.30%, in the same order. On other hand, FAT-12 strain was more sensitive to storage as compared to original strain, where the reduction rates were 35.60 and 35.75%, respectively for total viable cells and gassing power.

Keywords: Baker’s yeast, trehalose, glycogen, gassing power.

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Authors: Y. Al-Mahroqi, I.A. Metwally, A. Al-Hinai, A. Al-Badi

Abstract:

Losses reduction initiatives in distribution systems have been activated due to the increasing cost of supplying electricity, the shortage in fuel with ever-increasing cost to produce more power, and the global warming concerns. These initiatives have been introduced to the utilities in shape of incentives and penalties. Recently, the electricity distribution companies in Oman have been incentivized to reduce the distribution technical and non-technical losses with an equal annual reduction rate for 6 years. In this paper, different techniques for losses reduction in Mazoon Electricity Company (MZEC) are addressed. In this company, high numbers of substation and feeders were found to be non-compliant with the Distribution System Security Standard (DSSS). Therefore, 33 projects have been suggested to bring non-complying 29 substations and 28 feeders to meet the planed criteria and to comply with the DSSS. The largest part of MZEC-s network (South Batinah region) was modeled by ETAP software package. The model has been extended to implement the proposed projects and to examine their effects on losses reduction. Simulation results have shown that the implementation of these projects leads to a significant improvement in voltage profile, and reduction in the active and the reactive power losses. Finally, the economical analysis has revealed that the implementation of the proposed projects in MZEC leads to an annual saving of about US$ 5 million.

Keywords: Losses Reduction, Technical Losses, Non-Technical Losses, Cost Analysis

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Authors: Hong Li, Linfeng Li, Jianping Hu

Abstract:

With rapid technology scaling, the proportion of the static power consumption catches up with dynamic power consumption gradually. To decrease leakage consumption is becoming more and more important in low-power design. This paper presents a power-gating scheme for P-DTGAL (p-type dual transmission gate adiabatic logic) circuits to reduce leakage power dissipations under deep submicron process. The energy dissipations of P-DTGAL circuits with power-gating scheme are investigated in different processes, frequencies and active ratios. BSIM4 model is adopted to reflect the characteristics of the leakage currents. HSPICE simulations show that the leakage loss is greatly reduced by using the P-DTGAL with power-gating techniques.

Keywords: Leakage reduction, low power, deep submicronCMOS circuits, P-type adiabatic circuits.

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Authors: Amir Lotfi, Seyed Hamid Hosseini

Abstract:

During the recent past, due to the increase of electrical energy demand and governmental resources constraints in creating additional capacity in the generation, transmission, and distribution, privatization, and restructuring in electrical industry have been considered. So, in most of the countries, different parts of electrical industry like generation, transmission, and distribution have been separated in order to create competition. Considering these changes, environmental issues, energy growth, investment of private equity in energy generation units and difficulties of transmission lines expansion, distributed generation (DG) units have been used in power systems. Moreover, reduction in the need for transmission and distribution, the increase of reliability, improvement of power quality, and reduction of power loss have caused DG to be placed in power systems. On the other hand, considering low liquidity need, private investors tend to spend their money for DGs. In this project, the main goal is to offer an algorithm for planning and placing DGs in order to reduce the need for transmission and distribution network.

Keywords: Planning, transmission, distributed generation, power security, power systems.

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Authors: Sanjay Singh, M Sathish Kumar, H. S Mruthyunjaya

Abstract:

Multicarrier transmission system such as Orthogonal Frequency Division Multiplexing (OFDM) is a promising technique for high bit rate transmission in wireless communication systems. OFDM is a spectrally efficient modulation technique that can achieve high speed data transmission over multipath fading channels without the need for powerful equalization techniques. A major drawback of OFDM is the high Peak-to-Average Power Ratio (PAPR) of the transmit signal which can significantly impact the performance of the power amplifier. In this paper we have compared the PAPR reduction performance of Golay and Reed-Muller coded OFDM signal. From our simulation it has been found that the PAPR reduction performance of Golay coded OFDM is better than the Reed-Muller coded OFDM signal. Moreover, for the optimum PAPR reduction performance, code configuration for Golay and Reed-Muller codes has been identified.

Keywords: OFDM, PAPR, Perfect Codes, Golay Codes, Reed-Muller Codes

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Authors: G.V.K Murthy, S. Sivanagaraju, S. Satyanarayana, B. Hanumantha Rao

Abstract:

Distributed Generation (DG) systems are considered an integral part in future distribution system planning. Appropriate size and location of distributed generation plays a significant role in minimizing power losses in distribution systems. Among the benefits of distributed generation is the reduction in active power losses, which can improve the system performance, reliability and power quality. In this paper, Artificial Bee Colony (ABC) algorithm is proposed to determine the optimal DG-unit size and location by loss sensitivity index in order to minimize the real power loss, total harmonic distortion (THD) and voltage sag index improvement. Simulation study is conducted on 69-bus radial test system to verify the efficacy of the proposed method.

Keywords: Distributed generation, artificial bee colony method, loss reduction, radial distribution network.

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Authors: R. Srinivasa Rao

Abstract:

Individually Network reconfiguration or Capacitor control perform well in minimizing power loss and improving voltage profile of the distribution system. But for heavy reactive power loads network reconfiguration and for heavy active power loads capacitor placement can not effectively reduce power loss and enhance voltage profiles in the system. In this paper, an hybrid approach that combine network reconfiguration and capacitor placement using Harmony Search Algorithm (HSA) is proposed to minimize power loss reduction and improve voltage profile. The proposed approach is tested on standard IEEE 33 and 16 bus systems. Computational results show that the proposed hybrid approach can minimize losses more efficiently than Network reconfiguration or Capacitor control. The results of proposed method are also compared with results obtained by Simulated Annealing (SA). The proposed method has outperformed in terms of the quality of solution compared to SA.

Keywords: Capacitor Control, Network Reconfiguration, HarmonySearch Algorithm, Loss Reduction, Voltage Profile.

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Authors: P. Asadee

Abstract:

Multiplication algorithms have considerable effect on processors performance. A new high-speed, low-power multiplication algorithm has been presented using modified Dadda tree structure. Three important modifications have been implemented in inner product generation step, inner product reduction step and final addition step. Optimized algorithms have to be used into basic computation components, such as multiplication algorithms. In this paper, we proposed a new algorithm to reduce power, delay, and transistor count of a multiplication algorithm implemented using low power modified counter. This work presents a novel design for Dadda multiplication algorithms. The proposed multiplication algorithm includes structured parts, which have important effect on inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid adder is presented for fast, low voltage applications. The new 64-bit adder uses a new circuit to implement the proposed carry hybrid adder. The new adder using 80 nm CMOS technology has been implemented on 700 MHz clock frequency. The proposed multiplication algorithm has achieved 14 percent improvement in transistor count, 13 percent reduction in delay and 12 percent modification in power consumption in compared with conventional designs.

Keywords: adder, CMOS, counter, Dadda tree, encoder.

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Authors: K. Varesi

Abstract:

This paper proposes a Particle Swarm Optimization (PSO) based technique for the optimal allocation of Distributed Generation (DG) units in the power systems. In this paper our aim is to decide optimal number, type, size and location of DG units for voltage profile improvement and power loss reduction in distribution network. Two types of DGs are considered and the distribution load flow is used to calculate exact loss. Load flow algorithm is combined appropriately with PSO till access to acceptable results of this operation. The suggested method is programmed under MATLAB software. Test results indicate that PSO method can obtain better results than the simple heuristic search method on the 30-bus and 33- bus radial distribution systems. It can obtain maximum loss reduction for each of two types of optimally placed multi-DGs. Moreover, voltage profile improvement is achieved.

Keywords: Distributed Generation (DG), Optimal Allocation, Particle Swarm Optimization (PSO), Power Loss Minimization, Voltage Profile Improvement.

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Authors: Somaye Abdollahi Pour, Mohsen Saneei

Abstract:

This paper describes a novel monitoring scheme to minimize total active power in digital circuits depend on the demand frequency, by adjusting automatically both supply voltage and threshold voltages based on circuit operating conditions such as temperature, process variations, and desirable frequency. The delay monitoring results, will be control and apply so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. Design details of power monitor are examined using simulation framework in 32nm BTPM model CMOS process. Experimental results show the overhead of proposed circuit in terms of its power consumption is about 40 μW for 32nm technology; moreover the results show that our proposed circuit design is not far sensitive to the temperature variations and also process variations. Besides, uses the simple blocks which offer good sensitivity, high speed, the continuously feedback loop. This design provides up to 40% reduction in power consumption in active mode.

Keywords: active mode, delay monitor, body biasing, VDD scaling, low power.

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Authors: Alaa Al Hawari, Mohammad Khader, Wael El Hasan, Mahmoud Alijla, Ammar Manawi, Abdelbaki Benamour

Abstract:

The production of aluminum alloys and ingots – starting from the processing of alumina to aluminum, and the final cast product – was studied using a Life Cycle Assessment (LCA) approach. The studied aluminum supply chain consisted of a carbon plant, a reduction plant, a casting plant, and a power plant. In the LCA model, the environmental loads of the different plants for the production of 1 ton of aluminum metal were investigated. The impact of the aluminum production was assessed in eight impact categories. The results showed that for all of the impact categories the power plant had the highest impact only in the cases of Human Toxicity Potential (HTP) the reduction plant had the highest impact and in the Marine Aquatic Eco-Toxicity Potential (MAETP) the carbon plant had the highest impact. Furthermore, the impact of the carbon plant and the reduction plant combined was almost the same as the impact of the power plant in the case of the Acidification Potential (AP). The carbon plant had a positive impact on the environment when it come to the Eutrophication Potential (EP) due to the production of clean water in the process. The natural gas based power plant used in the case study had 8.4 times less negative impact on the environment when compared to the heavy fuel based power plant and 10.7 times less negative impact when compared to the hard coal based power plant.

Keywords: Life cycle assessment, aluminum production, Supply chain.

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Authors: Mayank Shakya, Soundra Pandian. K. K

Abstract:

A linear feedback shift register (LFSR) is proposed which targets to reduce the power consumption from within. It reduces the power consumption during testing of a Circuit Under Test (CUT) at two stages. At first stage, Control Logic (CL) makes the clocks of the switching units of the register inactive for a time period when output from them is going to be same as previous one and thus reducing unnecessary switching of the flip-flops. And at second stage, the LFSR reorders the test vectors by interchanging the bit with its next and closest neighbor bit. It keeps fault coverage capacity of the vectors unchanged but reduces the Total Hamming Distance (THD) so that there is reduction in power while shifting operation.

Keywords: Linear Feedback Shift Register, Total Hamming Distance, Fault Coverage, Control Logic

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Authors: N. Phanthuna, J. Jaturacherdchaiskul, S. Lerdvanittip, S. Auchariyamet

Abstract:

This paper proposes a particle swarm optimization (PSO) technique to solve the economic load dispatch (ELD) problems. For the ELD problem in this work, the objective function is to minimize the total fuel cost of all generator units for a given daily load pattern while the main constraints are power balance and generation output of each units. Case study in the test system of 40-generation units with 6 load patterns is presented to demonstrate the performance of PSO in solving the ELD problem. It can be seen that the optimal solution given by PSO provides the minimum total cost of generation while satisfying all the constraints and benefiting greatly from saving in power loss reduction.

Keywords: Particle Swarm Optimization, Economic Load Dispatch, Loss Reduction.

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Authors: Vinod Kumar Khera, R. K. Sharma, A. K. Gupta

Abstract:

Power dissipation increases exponentially during test mode as compared to normal operation of the circuit. In extreme cases, test power is more than twice the power consumed during normal operation mode. Test vector generation scheme is key component in deciding the power hungriness of a circuit during testing. Test vector count and consequent leakage current are functions of test vector generation scheme. Fault based test vector count optimization has been presented in this work. It helps in reducing test vector count and the leakage current. In the presented scheme, test vectors have been reduced by extracting essential child vectors. The scheme has been tested experimentally using stuck at fault models and results ensure the reduction in test vector count.

Keywords: Low power VLSI testing, independent fault, essential faults, test vector reduction.

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Authors: Abdulatif A. M. Shaban

Abstract:

Transient simulation of power electronic circuits is of considerable interest to the designer. The switching nature of the devices used permits development of specialized algorithms which allow a considerable reduction in simulation time compared to general purpose simulation algorithms. This paper describes a method used to simulate a power electronic circuits using the SIMULINK toolbox within MATLAB software. Theoretical results are presented provides the basis of transient analysis of a power electronic circuits.

Keywords: Modelling, Simulation.

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Authors: Jyothi Digge, B. U. Rindhe, S. K. Narayankhedkar

Abstract:

A compact 1x3 power splitter based on Photonic Crystal Waveguides (PCW) with flexible power splitting ratio is presented in this paper. Multimode interference coupler (MMI) is integrated with PCW. The device size reduction compared with the conventional MMI power splitter is attributed to the large dispersion of the PCW. Band Solve tool is used to calculate the band structure of PCW. Finite Difference Time Domain (FDTD) method is adopted to simulate the relevant structure at 1550nm wavelength. The device is polarization insensitive and allows the control of output (o/p) powers within certain percentage points for both polarizations.

Keywords: Dispersion, MMI Coupler, Photonic Bandgap, Power Splitter.

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Authors: Toshiaki Yanada, Kazumi Ishikawa

Abstract:

The present paper deals with the analysis and development of noise-reduction transformer that has a filter function for conductive noise transmission. Two types of prototype noise-reduction transformers with two different output voltages are proposed. To determine an optimum design for the noise-reduction transformer, noise attenuation characteristics are discussed based on the experiments and the equivalent circuit analysis. The analysis gives a relation between the circuit parameters and the noise attenuation. High performance step-down noise-reduction transformer for direct power supply to electronics equipment is developed. The input voltage of the transformer is 100 V and the output voltage is 5 V. Frequency characteristics of noise attenuation are discussed, and prevention of pulse noise transmission is demonstrated. Normal mode noise attenuation of this transformer is –80 dB, and common mode exceeds –90 dB. The step-down noise-reduction transformer eliminates pulse noise efficiently.

Keywords: conductive noise, EMC, EMI, noise attenuation, transformer.

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Authors: Md. Asif Jahangir Chowdhury, Md. Shahriar Rizwan, M. S. Islam

Abstract:

In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance.

Keywords: variable body biasing, state saving technique, stack effect, dual V-th, static power reduction.

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Authors: Theodore Grosch, Felipe Koji Godinho Hoshino

Abstract:

In wireless communications, 3GPP LTE is one of the solutions to meet the greater transmission data rate demand. One issue inherent to this technology is the PAPR (Peak-to-Average Power Ratio) of OFDM (Orthogonal Frequency Division Multiplexing) modulation. This high PAPR affects the efficiency of power amplifiers. One approach to mitigate this effect is the Crest Factor Reduction (CFR) technique. In this work, we simulate the impact of Hard Limited Clipping Crest Factor Reduction technique on BER (Bit Error Rate) in OFDM based Systems. In general, the results showed that CFR has more effects on higher digital modulation schemes, as expected. More importantly, we show the worst-case degradation due to CFR on QPSK, 16QAM, and 64QAM signals in a linear system. For example, hard clipping of 9 dB results in a 2 dB increase in signal to noise energy at a 1% BER for 64-QAM modulation.

Keywords: Bit error rate, crest factor reduction, OFDM, physical layer simulation.

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Authors: Ei Ei Phyu, Kyaw Myo Lin, Thin Thin Moe

Abstract:

The paper presents an approach to improve the reliability and reduce line losses of practical distribution system applying network reconfiguration. The change of the topology redirects the power flow within the distribution network to obtain better performance of the system. Practical distribution network (Pyigyitagon Industrial Zone (I)) is used as the case study network. The detailed calculations of the reliability indices are done by using analytical method and power flow calculation is performed by Newton-Rephason solver. The comparison of various network reconfiguration techniques are described with respect to power loss and reliability index levels. Finally, the optimal reconfigured network is selected among difference cases based on the two factors: the most reliable network and the least loss minimization.

Keywords: Distribution system reliability, loss reduction, network reconfiguration, reliability enhancement, reliability indices.

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