Search results for: pipeline processor

Authors: Mohammad S. Laghari, Gulzar A. Khuwaja

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Many problems in computer vision and image processing present potential for parallel implementations through one of the three major paradigms of geometric parallelism, algorithmic parallelism and processor farming. Static process scheduling techniques are used successfully to exploit geometric and algorithmic parallelism, while dynamic process scheduling is better suited to dealing with the independent processes inherent in the process farming paradigm. This paper considers the application of parallel or multi-computers to a class of problems exhibiting spatial data characteristic of the geometric paradigm. However, by using processor farming paradigm, a dynamic scheduling technique is developed to suit the MIMD structure of the multi-computers. A hybrid scheme of scheduling is also developed and compared with the other schemes. The specific problem chosen for the investigation is the Hough transform for line detection.

Keywords: Hough transforms, parallel computer, parallel paradigms, scheduling.

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Authors: Shiji Hu, Lei Li, Wanting Zhou, Daohong Yang

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The data encryption is the foundation of today’s communication. On this basis, to improve the speed of data encryption and decryption is always an important goal for high-speed applications. This paper proposed an elliptic curve crypto processor architecture based on SM2 prime field. Regarding hardware implementation, we optimized the algorithms in different stages of the structure. For modulo operation on finite field, we proposed an optimized improvement of the Karatsuba-Ofman multiplication algorithm and shortened the critical path through the pipeline structure in the algorithm implementation. Based on SM2 recommended prime field, a fast modular reduction algorithm is used to reduce 512-bit data obtained from the multiplication unit. The radix-4 extended Euclidean algorithm was used to realize the conversion between the affine coordinate system and the Jacobi projective coordinate system. In the parallel scheduling point operations on elliptic curves, we proposed a three-level parallel structure of point addition and point double based on the Jacobian projective coordinate system. Combined with the scalar multiplication algorithm, we added mutual pre-operation to the point addition and double point operation to improve the efficiency of the scalar point multiplication. The proposed ECC hardware architecture was verified and implemented on Xilinx Virtex-7 and ZYNQ-7 platforms, and each 256-bit scalar multiplication operation took 0.275ms. The performance for handling scalar multiplication is 32 times that of CPU (dual-core ARM Cortex-A9).

Keywords: Elliptic curve cryptosystems, SM2, modular multiplication, point multiplication.

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Authors: Toshitaka Higashino, Naoki Wakamiya

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Human beings perform a task by perceiving information from outside, recognizing them, and responding them. There have been various attempts to analyze and understand internal processes behind the reaction to a given stimulus by conducting psychological experiments and analysis from multiple perspectives. Among these, we focused on Model Human Processor (MHP). However, it was built based on psychological experiments and thus the relation with brain activity was unclear so far. To verify the validity of the MHP and propose our model from a viewpoint of neuroscience, EEG (Electroencephalography) measurements are performed during experiments in this study. More specifically, first, experiments were conducted where Latin alphabet characters were used as visual stimuli. In addition to response time, ERPs (event-related potentials) such as N100 and P300 were measured by using EEG. By comparing cycle time predicted by the MHP and latency of ERPs, it was found that N100, related to perception of stimuli, appeared at the end of the perceptual processor. Furthermore, by conducting an additional experiment, it was revealed that P300, related to decision making, appeared during the response decision process, not at the end. Second, by experiments using Japanese Hiragana characters, i.e. Japan's own phonetic symbols, those findings were confirmed. Finally, Japanese Kanji characters were used as more complicated visual stimuli. A Kanji character usually has several readings and several meanings. Despite the difference, a reading-related task and a meaning-related task exhibited similar results, meaning that they involved similar information processing processes of the brain. Based on those results, our model was proposed which reflects response time and ERP latency. It consists of three processors: the perception processor from an input of a stimulus to appearance of N100, the cognitive processor from N100 to P300, and the decision-action processor from P300 to response. Using our model, an application system which reflects brain activity can be established.

Keywords: Brain activity, EEG, information processing model, model human processor.

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Authors: I. Abuiziah, A. Oulhaj, K. Sebari, D. Ouazar

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Desurging tank with automatic air control “DTAAC” is a water hammer protection device, operates either an open or closed surge tank according to the water level inside the surge tank, with the volume of air trapped in the filling phase, this protection device has the advantages of its easy maintenance, and does not need to run any external energy source (air compressor). A computer program has been developed based on the characteristic method to simulate flow transient phenomena in pressurized water pipeline systems, it provides the influence of using the protection devices to control the adverse effects due to excessive and low pressure occurring in this phenomena. The developed model applied to a simple main water pipeline system: pump combined with DTAAC connected to a reservoir.  The results obtained provide that the model is an efficient tool for water hammer analysis. Moreover; using the DTAAC reduces the unfavorable effects of the transients.

Keywords: DTAAC, Flow transient, Numerical model, Pipeline system, Protection devices.

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Authors: Danesh Nourzadeh, Sepideh Khorshid, Shiro Takada, Khosrow Bargi

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In this paper, transversal vibration of buried pipelines during loading induced by underground explosions is analyzed. The pipeline is modeled as an infinite beam on an elastic foundation, so that soil-structure interaction is considered by means of transverse linear springs along the pipeline. The pipeline behavior is assumed to be ideal elasto-plastic which an ultimate strain value limits the plastic behavior. The blast loading is considered as a point load, considering the affected length at some point of the pipeline, in which the magnitude decreases exponentially with time. A closed-form solution for the quasi-static problem is carried out for both elastic and elasticperfect plastic behaviors of pipe materials. At the end, a comparative study on steel and polyethylene pipes with different sizes buried in various soil conditions, affected by a predefined underground explosion is conducted, in which effect of each parameter is discussed.

Keywords: Beam on elastic foundation, Buried pipelines, External explosion, Non-linear quasi-static solution.

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Authors: Faizal A. Samman, Thomas Hollstein, Manfred Glesner

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This paper presents design trade-off and performance impacts of the amount of pipeline phase of control path signals in a wormhole-switched network-on-chip (NoC). The numbers of the pipeline phase of the control path vary between two- and one-cycle pipeline phase. The control paths consist of the routing request paths for output selection and the arbitration paths for input selection. Data communications between on-chip routers are implemented synchronously and for quality of service, the inter-router data transports are controlled by using a link-level congestion control to avoid lose of data because of an overflow. The trade-off between the area (logic cell area) and the performance (bandwidth gain) of two proposed NoC router microarchitectures are presented in this paper. The performance evaluation is made by using a traffic scenario with different number of workloads under 2D mesh NoC topology using a static routing algorithm. By using a 130-nm CMOS standard-cell technology, our NoC routers can be clocked at 1 GHz, resulting in a high speed network link and high router bandwidth capacity of about 320 Gbit/s. Based on our experiments, the amount of control path pipeline stages gives more significant impact on the NoC performance than the impact on the logic area of the NoC router.

Keywords: Network-on-Chip, Synchronous Parallel Pipeline, Router Architecture, Wormhole Switching

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Authors: Yukinari Minagi , Akinori Kanasugi

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This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operation. The proposed arithmetic circuit performs floating-point arithmetic which is frequently used in science and technology. The data format is floating-point based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

Keywords: dynamic reconfiguration, floating-point arithmetic, double precision, FPGA

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Authors: I. Abuiziah, A. Oulhaj, K. Sebari, D. Ouazar

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This paper presents the problem of modeling and simulating of transient phenomena in conveying pipeline systems based on the rigid column and full elastic methods. Transient analysis is important and one of the more challenging and complicated flow problem in the design and the operation of water pipeline systems. Transient can produce large pressure forces and rapid fluid acceleration into a water pipeline system, these disturbances may result in device failures, system fatigue or pipe ruptures, and even the dirty water intrusion. Several methods have been introduced and used to analyze transient flow, an accurate analysis and suitable protection devices should be used to protect water pipeline systems. The fourth-order Runge-Kutta method has been used to solve the dynamic and continuity equations in the rigid column method, while the characteristics method used to solve these equations in the full elastic method. The results obtained provide that the model is an efficient tool for flow transient analysis and provide approximately identical results by using these two methods. Moreover; using the simple surge tank ”open surge tank” reduces the unfavorable effects of transients.

Keywords: Elastic method, Flow transient, Open surge tank, Pipeline, Protection devices, Numerical model, Rigid column method.

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Authors: Omid Adibi, Nategheh Najafpour, Bijan Farhanieh, Hossein Afshin

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Energy transmission pipelines are one of the most vital parts of each country which several strict laws have been conducted to enhance the safety of these lines and their vicinity. One of these laws is the safety distance around high pressure gas pipelines. Safety distance refers to the minimum distance from the pipeline where people and equipment do not confront with serious damages. In the present study, safety distance around high pressure gas transmission pipelines were determined by using numerical methods. For this purpose, gas leakages from cracked pipeline and created jet fires were simulated as continuous ignition, three dimensional, unsteady and turbulent cases. Numerical simulations were based on finite volume method and turbulence of flow was considered using k-ω SST model. Also, the combustion of natural gas and air mixture was applied using the eddy dissipation method. The results show that, due to the high pressure difference between pipeline and environment, flow chocks in the cracked area and velocity of the exhausted gas reaches to sound speed. Also, analysis of the incident radiation results shows that safety distances around 42 inches high pressure natural gas pipeline based on 5 and 15 kW/m² criteria are 205 and 272 meters, respectively.

Keywords: Gas pipelines, incident radiation, numerical simulation, safety distance.

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Authors: Jahangir Jafari, Nematollah Khorasani, Afshin Danehkar

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Having a very many number of pipelines all over the country, Iran is one of the countries consists of various ecosystems with variable degrees of fragility and robusticity as well as geographical conditions. This study presents a state-of-the-art method to estimate environmental risks of pipelines by recommending rational equations including FES, URAS, SRS, RRS, DRS, LURS and IRS as well as FRS to calculate the risks. This study was carried out by a relative semi-quantitative approach based on land uses and HVAs (High-Value Areas). GIS as a tool was used to create proper maps regarding the environmental risks, land uses and distances. The main logic for using the formulas was the distance-based approaches and ESI as well as intersections. Summarizing the results of the study, a risk geographical map based on the ESIs and final risk score (FRS) was created. The study results showed that the most sensitive and so of high risk area would be an area comprising of mangrove forests located in the pipeline neighborhood. Also, salty lands were the most robust land use units in the case of pipeline failure circumstances. Besides, using a state-of-the-art method, it showed that mapping the risks of pipelines out with the applied method is of more reliability and convenience as well as relative comprehensiveness in comparison to present non-holistic methods for assessing the environmental risks of pipelines. The focus of the present study is “assessment" than that of “management". It is suggested that new policies are to be implemented to reduce the negative effects of the pipeline that has not yet been constructed completely

Keywords: ERM, ESI, ERA, Pipeline, Assalouyeh

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Authors: Ahmed Madian, Muaz Aljarhi

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Coordinate Rotation Digital Computer (CORDIC) is a unique digital computing unit intended for the computation of mathematical operations and functions. This paper presents A multi CORDIC processor that integrates different CORDIC architectures on a single FPGA chip and allows the user to select the CORDIC architecture to proceed with based on what he wants to calculate and his needs. Synthesis show that radix 2 CORDIC has the lowest clock delay, radix 8 CORDIC has the highest LUT usage and lowest register usage while Hybrid Radix 4 CORDIC had the highest clock delay.

Keywords: Multi, CORDIC, FPGA, Processor.

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Authors: Hamed Homaei, Iraj Mahdavi, Ali Tajdin

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One of the main concerns of miners is to increase the quality level of their products because the mining metals price depends on their quality level; however, increasing the quality level of these products has different costs at different levels of the supply chain. These costs usually increase after extractor level. This paper studies the coordination issue of a decentralized three-level supply chain with one supplier (extractor), one mineral processor and one manufacturer in which the increasing product quality level cost at the processor level is higher than the supplier and at the level of the manufacturer is more than the processor. We identify the optimal product quality level for each supply chain member by designing a revenue sharing contract. Finally, numerical examples show that the designed contract not only increases the final product quality level but also provides a win-win condition for all supply chain members and increases the whole supply chain profit.

Keywords: Three-stage supply chain, product quality improvement, channel coordination, revenue sharing.

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Authors: Kwang Y. Lee, Tae R. Park, Jae C. Kwak, Yong S. Koo

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When a small H/W IP is designed, we can develop an appropriate verification environment by observing the simulated signal waves, or using the serial test vectors for the fixed output. In the case of design and verification of a massive parallel processor with multiple IPs, it-s difficult to make a verification system with existing common verification environment, and to verify each partial IP. A TestDrive verification environment can build easy and reliable verification system that can produce highly intuitive results by applying Modelsim and SystemVerilog-s DPI. It shows many advantages, for example a high-level design of a GPGPU processor design can be migrate to FPGA board immediately.

Keywords: Virtual Simulation, Verification, IP Design, GPGPU

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Authors: S. S. Dol, M. S. Chan, S. F. Wong, J. S. Lim

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Emulsion formation is unavoidable and can be detrimental to an oil field production. The presence of stable emulsions also reduces the quality of crude oil and causes more problems in the downstream refinery operations, such as corrosion and pipeline pressure drop. Hence, it is important to know the effects of emulsions in the pipeline. Light crude oil was used for the continuous phase in the W/O emulsions where the emulsions pass through a flow loop to test the pressure drop across the pipeline. The results obtained shows that pressure drop increases as water cut is increased until it peaks at the phase inversion of the W/O emulsion between 30% to 40% water cut. Emulsions produced by gradual constrictions show a lower stability as compared to sudden constrictions. Lower stability of emulsions in gradual constriction has the higher influence of pressure drop compared to a sudden sharp decrease in diameter in sudden constriction. Generally, sudden constriction experiences pressure drop of 0.013% to 0.067% higher than gradual constriction of the same ratio. Lower constriction ratio cases cause larger pressure drop ranging from 0.061% to 0.241%. Considering the higher profitability in lower emulsion stability and lower pressure drop at the developed flow region of different constrictions, an optimum design of constriction is found to be gradual constriction with a ratio of 0.5.

Keywords: Constriction, pressure drop, turbulence, water cut, water-in-oil emulsions.

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Authors: K. S. Lim, S. N. A. Azraai, N. M. Noor, N. Yahaya

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Polymeric composites are being increasingly used as repair material for repairing critical infrastructures such as building, bridge, pressure vessel, piping and pipeline. Technique in repairing damaged pipes is one of the major concerns of pipeline owners. Considerable researches have been carried out on the repair of corroded pipes using composite materials. This article attempts a short review of the subject matter to provide insight into various techniques used in repairing corroded pipes, focusing on a wide range of composite repair systems. These systems including pre-cured layered, flexible wet lay-up, pre-impregnated, split composite sleeve and flexible tape systems. Both advantages and limitations of these repair systems were highlighted. Critical technical aspects have been discussed through the current standards and practices. Research gaps and future study scopes in achieving more effective design philosophy are also presented.

Keywords: Composite materials, pipeline, repair technique, polymers.

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Authors: Emilija Miletic, Milos Krstic, Maxim Piz, Michael Methfessel

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In this work we present a solution for DAGC (Digital Automatic Gain Control) in WLAN receivers compatible to IEEE 802.11a/g standard. Those standards define communication in 5/2.4 GHz band using Orthogonal Frequency Division Multiplexing OFDM modulation scheme. WLAN Transceiver that we have used enables gain control over Low Noise Amplifier (LNA) and a Variable Gain Amplifier (VGA). The control over those signals is performed in our digital baseband processor using dedicated hardware block DAGC. DAGC in this process is used to automatically control the VGA and LNA in order to achieve better signal-to-noise ratio, decrease FER (Frame Error Rate) and hold the average power of the baseband signal close to the desired set point. DAGC function in baseband processor is done in few steps: measuring power levels of baseband samples of an RF signal,accumulating the differences between the measured power level and actual gain setting, adjusting a gain factor of the accumulation, and applying the adjusted gain factor the baseband values. Based on the measurement results of RSSI signal dependence to input power we have concluded that this digital AGC can be implemented applying the simple linearization of the RSSI. This solution is very simple but also effective and reduces complexity and power consumption of the DAGC. This DAGC is implemented and tested both in FPGA and in ASIC as a part of our WLAN baseband processor. Finally, we have integrated this circuit in a compact WLAN PCMCIA board based on MAC and baseband ASIC chips designed from us.

Keywords: WLAN, AGC, RSSI, baseband processor

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Authors: Anju S. Pillai, T.B. Isha

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With the necessity of increased processing capacity with less energy consumption; power aware multiprocessor system has gained more attention in the recent future. One of the additional challenges that is to be solved in a multi-processor system when compared to uni-processor system is job allocation. This paper presents a novel task dependent job allocation algorithm: Energy centric- Allocation (Ec-A) and Rate Monotonic (RM) scheduling to minimize energy consumption in a multiprocessor system. A simulation analysis is carried out to verify the performance increase with reduction in energy consumption and required number of processors in the system.

Keywords: Energy consumption, Job allocation, Multiprocessor systems, Task dependent.

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Authors: Iman Zangeneh, Mostafa Moradi, Mazyar Baranpouyan

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System is using multiple processors for computing and information processing, is increasing rapidly speed operation of these systems compared with single processor systems, very significant impact on system performance is increased .important differences to yield a single multi-processor cpu, the scheduling policies, to reduce the implementation time of all processes. Notwithstanding the famous algorithms such as SPT, LPT, LSPT and RLPT for scheduling and there, but none led to the answer are not optimal.In this paper scheduling using genetic algorithms and innovative way to finish the whole process faster that we do and the result compared with three algorithms we mentioned.

Keywords: Multiprocessor system, genetic algorithms, time implementation process.

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Authors: Niveditha Domse, Kris Kumar, K. N. Balasubramanya Murthy

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The more recent satellite projects/programs makes extensive usage of real – time embedded systems. 16 bit processors which meet the Mil-Std-1750 standard architecture have been used in on-board systems. Most of the Space Applications have been written in ADA. From a futuristic point of view, 32 bit/ 64 bit processors are needed in the area of spacecraft computing and therefore an effort is desirable in the study and survey of 64 bit architectures for space applications. This will also result in significant technology development in terms of VLSI and software tools for ADA (as the legacy code is in ADA). There are several basic requirements for a special processor for this purpose. They include Radiation Hardened (RadHard) devices, very low power dissipation, compatibility with existing operational systems, scalable architectures for higher computational needs, reliability, higher memory and I/O bandwidth, predictability, realtime operating system and manufacturability of such processors. Further on, these may include selection of FPGA devices, selection of EDA tool chains, design flow, partitioning of the design, pin count, performance evaluation, timing analysis etc. This project deals with a brief study of 32 and 64 bit processors readily available in the market and designing/ fabricating a 64 bit RISC processor named RISC MicroProcessor with added functionalities of an extended double precision floating point unit and a 32 bit signal processing unit acting as co-processors. In this paper, we emphasize the ease and importance of using Open Core (OpenSparc T1 Verilog RTL) and Open “Source" EDA tools such as Icarus to develop FPGA based prototypes quickly. Commercial tools such as Xilinx ISE for Synthesis are also used when appropriate.

Keywords: RISC MicroProcessor, RPC – RISC Processor Core, PBX – Processor to Block Interface part of the Interconnection Network, BPX – Block to Processor Interface part of the Interconnection Network, FPU – Floating Point Unit, SPU – Signal Processing Unit, WB – Wishbone Interface, CTU – Clock and Test Unit

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Authors: Hironori Kakuta, Kajiro Watanabe, Yosuke Kurihara

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Water leakage is a serious problem in the maintenance of a waterworks facility. Monitoring the water flow rate is one way to locate leakage. However, conventional flowmeters such as the wet-type flowmeter and the clamp-on type ultrasonic flowmeter require additional construction for their installation and are therefore quite expensive. This paper proposes a novel estimation system for the flow rate in a water pipeline, which employs a vibration sensor. This assembly can be attached to any water pipeline without the need for additional high-cost construction. The vibration sensor is designed based on a condenser microphone. This sensor detects vibration caused by water flowing through a pipeline. It is possible to estimate the water flow rate by measuring the amplitude of the output signal from the vibration sensor. We confirmed the validity of the proposed sensing system experimentally.

Keywords: Condenser microphone, Flow rate estimation, Piping vibration, Water pipe.

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Authors: Christos Meletis, Paul Bougas, George Economakos , Paraskevas Kalivas, Kiamal Pekmestzi

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In this paper, we propose a new architecture for the implementation of the N-point Fast Fourier Transform (FFT), based on the Radix-2 Decimation in Frequency algorithm. This architecture is based on a pipeline circuit that can process a stream of samples and produce two FFT transform samples every clock cycle. Compared to existing implementations the architecture proposed achieves double processing speed using the same circuit complexity.

Keywords: Digital signal processing, systolic circuits, FFTalgorithm.

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Authors: Chih-Wei Hsieh, Chau-Yi Chou, Sheng-HsiuKuo, Tsung-Che Tsai, I-Chen Wu

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This paper presents the benchmarking results and performance evaluation of differentclustersbuilt atthe National Center for High-Performance Computingin Taiwan. Performance of processor, memory subsystem andinterconnect is a critical factor in the overall performance of high performance computing platforms. The evaluation compares different system architecture and software platforms. Most supercomputer used HPL to benchmark their system performance, in accordance with the requirement of the TOP500 List. In this paper we consider system memory access factors that affect benchmark performance, such as processor and memory performance.We hope these works will provide useful information for future development and construct cluster system.

Keywords: Performance Evaluation, Benchmarking and High-Performance Computing

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Authors: Hwan Su Jung, Ahn Jun Gil, Jong Tae Kim

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Power management techniques are necessary to save power in the microprocessor. By changing the frequency and/or operating voltage of processor, DVFS can control power consumption. In this paper, we perform a case study to find optimal power state transition for DVFS. We propose the equation to find the optimal ratio between executions of states while taking into account the deadline of processing time and the power state transition delay overhead. The experiment is performed on the Cortex-M4 processor, and average 6.5% power saving is observed when DVFS is applied under the deadline condition.

Keywords: Deadline, Dynamic Voltage Frequency Scaling, Power State Transition.

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Authors: Wisuwat Plodpradista

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Tubular linear induction motor (TLIM) can be used as a capsule pump in a large pneumatic capsule pipeline (PCP) system. Parametric performance evaluation of the designed 1-meter diameter PCP-TLIM system yields encouraging results for practical implementation. The capsule thrust and speed inside the TLIM pump can be calculated from the combination of the PCP fluid mechanics and the TLIM equations. The TLIM equivalent circuits derived from those of the conventional three-phase induction motor are used as a model to predict the static test results of a small-scale PCP-TLIM system. In this paper, additional dynamic tests are performed on the same small-scale PCP-TLIM system with two capsules of different diameters. The behaviors of the capsule inside the pump are observed and analyzed. The dynamic performances from the dynamic tests are compared with the theoretical predictions based on the TLIM equivalent circuit model.

Keywords: Pneumatic capsule pipeline, Tubular linear induction motor

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Authors: Nael Y. Zabel, Maged E. Georgy, Moheeb E. Ibrahim

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A knowledge-based expert system with the acronym RASPE is developed as an application tool to help decision makers in construction companies make informed decisions about managing risks in pipeline construction projects. Choosing to use expert systems from all available artificial intelligence techniques is due to the fact that an expert system is more suited to representing a domain’s knowledge and the reasoning behind domain-specific decisions. The knowledge-based expert system can capture the knowledge in the form of conditional rules which represent various project scenarios and potential risk mitigation/response actions. The built knowledge in RASPE is utilized through the underlying inference engine that allows the firing of rules relevant to a project scenario into consideration. Paper provides an overview of the knowledge acquisition process and goes about describing the knowledge structure which is divided up into four major modules. The paper shows one module in full detail for illustration purposes and concludes with insightful remarks.

Keywords: Expert System, Knowledge Management, Pipeline Projects, Risk Mismanagement.

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Authors: Anand B. Desamala, Ashok Kumar Dasamahapatra, Tapas K. Mandal

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In the present work, detailed analysis on flow characteristics of a pair of immiscible liquids through horizontal pipeline is simulated by using ANSYS FLUENT 6.2. Moderately viscous oil and water (viscosity ratio = 107, density ratio = 0.89 and interfacial tension = 0.024 N/m) have been taken as system fluids for the study. Volume of Fluid (VOF) method has been employed by assuming unsteady flow, immiscible liquid pair, constant liquid properties, and co-axial flow. Meshing has been done using GAMBIT. Quadrilateral mesh type has been chosen to account for the surface tension effect more accurately. From the grid independent study, we have selected 47037 number of mesh elements for the entire geometry. Simulation successfully predicts slug, stratified wavy, stratified mixed and annular flow, except dispersion of oil in water, and dispersion of water in oil. Simulation results are validated with horizontal literature data and good conformity is observed. Subsequently, we have simulated the hydrodynamics (viz., velocity profile, area average pressure across a cross section and volume fraction profile along the radius) of stratified wavy and annular flow at different phase velocities. The simulation results show that in the annular flow, total pressure of the mixture decreases with increase in oil velocity due to the fact that pipe cross section is completely wetted with water. Simulated oil volume fraction shows maximum at the centre in core annular flow, whereas, in stratified flow, maximum value appears at upper side of the pipeline. These results are in accord with the actual flow configuration. Our findings could be useful in designing pipeline for transportation of crude oil.

Keywords: CFD, Horizontal pipeline, Oil-water flow, VOF technique.

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Authors: Choon Ki Ahn, Jung Hun Park, Wook Hyun Kwon

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CEMTool is a command style design and analyzing package for scientific and technological algorithm and a matrix based computation language. In this paper, we present new 2D & 3D finite element method (FEM) packages for CEMTool. We discuss the detailed structures and the important features of pre-processor, solver, and post-processor of CEMTool 2D & 3D FEM packages. In contrast to the existing MATLAB PDE Toolbox, our proposed FEM packages can deal with the combination of the reserved words. Also, we can control the mesh in a very effective way. With the introduction of new mesh generation algorithm and fast solving technique, our FEM packages can guarantee the shorter computational time than MATLAB PDE Toolbox. Consequently, with our new FEM packages, we can overcome some disadvantages or limitations of the existing MATLAB PDE Toolbox.

Keywords: CEMTool, Finite element method (FEM), Numericalanalysis, Partial differential equation (PDE)

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Authors: Seung You Na, Daejung Shin, Jin Young Kim, Seong-Joon Baek, Bae-Ho Lee

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Recently there has been a growing interest in the field of bio-mimetic robots that resemble the behaviors of an insect or an aquatic animal, among many others. One of various bio-mimetic robot applications is to explore pipelines, spotting any troubled areas or malfunctions and reporting its data. Moreover, the robot is able to prepare for and react to any abnormal routes in the pipeline. Special types of mobile robots are necessary for the pipeline monitoring tasks. In order to move effectively along a pipeline, the robot-s movement will resemble that of insects or crawling animals. When situated in massive pipelines with complex routes, the robot places fixed sensors in several important spots in order to complete its monitoring. This monitoring task is to prevent a major system failure by preemptively recognizing any minor or partial malfunctions. Areas uncovered by fixed sensors are usually impossible to provide real-time observation and examination, and thus are dependent on periodical offline monitoring. This paper proposes a monitoring system that is able to monitor the entire area of pipelines–with and without fixed sensors–by using the bio-mimetic robot.

Keywords: Bio-mimetic robots, Plant pipes monitoring, Mobile and active monitoring.

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Authors: Ezequiel Herruzo, Juan José Cruz, José Ignacio Benavides, Oscar Plata

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This paper describes a new algorithm of arrangement in parallel, based on Odd-Even Mergesort, called division and concurrent mixes. The main idea of the algorithm is to achieve that each processor uses a sequential algorithm for ordering a part of the vector, and after that, for making the processors work in pairs in order to mix two of these sections ordered in a greater one, also ordered; after several iterations, the vector will be completely ordered. The paper describes the implementation of the new algorithm on a Message Passing environment (such as MPI). Besides, it compares the obtained experimental results with the quicksort sequential algorithm and with the parallel implementations (also on MPI) of the algorithms quicksort and bitonic sort. The comparison has been realized in an 8 processors cluster under GNU/Linux which is running on a unique PC processor.

Keywords: Parallel algorithm, arrangement, MPI, sorting, parallel program.

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Authors: Yoshiaki Shikata, Nobutane Hanayama

Abstract:

We present a prioritized, limited multi-server processor sharing (PS) system where each server has various capacities, and N (≥2) priority classes are allowed in each PS server. In each prioritized, limited server, different service ratio is assigned to each class request, and the number of requests to be processed is limited to less than a certain number. Routing strategies of such prioritized, limited multi-server PS systems that take into account the capacity of each server are also presented, and a performance evaluation procedure for these strategies is discussed. Practical performance measures of these strategies, such as loss probability, mean waiting time, and mean sojourn time, are evaluated via simulation. In the PS server, at the arrival (or departure) of a request, the extension (shortening) of the remaining sojourn time of each request receiving service can be calculated by using the number of requests of each class and the priority ratio. Utilising a simulation program which executes these events and calculations, the performance of the proposed prioritized, limited multi-server PS rule can be analyzed. From the evaluation results, most suitable routing strategy for the loss or waiting system is clarified.

Keywords: Processor sharing, multi-server, various capacity, N priority classes, routing strategy, loss probability, mean sojourn time, mean waiting time, simulation.

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