Commenced in January 2007
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A Virtual Simulation Environment for a Design and Verification of a GPGPU

Authors: Kwang Y. Lee, Tae R. Park, Jae C. Kwak, Yong S. Koo

Abstract:

When a small H/W IP is designed, we can develop an appropriate verification environment by observing the simulated signal waves, or using the serial test vectors for the fixed output. In the case of design and verification of a massive parallel processor with multiple IPs, it-s difficult to make a verification system with existing common verification environment, and to verify each partial IP. A TestDrive verification environment can build easy and reliable verification system that can produce highly intuitive results by applying Modelsim and SystemVerilog-s DPI. It shows many advantages, for example a high-level design of a GPGPU processor design can be migrate to FPGA board immediately.

Keywords: Virtual Simulation, Verification, IP Design, GPGPU

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1075675

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References:


[1] http://www.systemverilog.org
[2] http://www.doulos.com/knowhow/sysverilog/tutorial/dpi
[3] Hyungki Jeong, Kwang Yeob Lee and Jae Chang Kwak,"Test-Drive System for a Design & Verification of a GP-GPU Processor," 2010 SoC Conference, The institute of Electronics Engineering of Korea, April 2010, pp.40-43
[4] GPGPU, General Purpose Computation Using Graphics Hardware, http://www.gpgpu.org
[5] Hyungki Jeong, Kwang Yeob Lee and Jae Chang Kwak,"A Multi-thread Processor Architecture with Dual Phase Variable-Length Instructions," ITC-CSCC2008, July 2008, pp.209-212.
[6] Kwang Yeob Lee, Tae Ryoung Park, Jae Chang Kwak, Yong Seo Koo,"A Design of Multi-threaded Shader Processor with Dual-Phase Pipeline Architecture," The First international Conference on Advances in Multimedia MMEDIA 2009, 20-25 July 2009 colmar, France, pp 121-124.
[7] S. Ryoo, C. I. Rodrigues, S.S. Stone, S.S. Baghsorkhi, S.Z. Ueng, J.A. Stratton, and W.W. Hwu,"Program optimization space pruning for a multithreaded GPU," in Proceedings of the 2008 International Symposium on Code Generation and Optimization, April 2008, pp. 195-204.