@article{(Open Science Index):https://publications.waset.org/pdf/10666,
	  title     = {A Virtual Simulation Environment for a Design and Verification of a GPGPU},
	  author    = {Kwang Y. Lee and  Tae R. Park and  Jae C. Kwak and  Yong S. Koo},
	  country	= {},
	  institution	= {},
	  abstract     = {When a small H/W IP is designed, we can develop an
appropriate verification environment by observing the simulated
signal waves, or using the serial test vectors for the fixed output. In the
case of design and verification of a massive parallel processor with
multiple IPs, it-s difficult to make a verification system with existing
common verification environment, and to verify each partial IP. A
TestDrive verification environment can build easy and reliable
verification system that can produce highly intuitive results by
applying Modelsim and SystemVerilog-s DPI. It shows many
advantages, for example a high-level design of a GPGPU processor
design can be migrate to FPGA board immediately.},
	    journal   = {International Journal of Computer and Information Engineering},
	  volume    = {5},
	  number    = {6},
	  year      = {2011},
	  pages     = {611 - 615},
	  ee        = {https://publications.waset.org/pdf/10666},
	  url   	= {https://publications.waset.org/vol/54},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 54, 2011},