%0 Journal Article
	%A Kwang Y. Lee and  Tae R. Park and  Jae C. Kwak and  Yong S. Koo
	%D 2011
	%J International Journal of Computer and Information Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 54, 2011
	%T A Virtual Simulation Environment for a Design and Verification of a GPGPU
	%U https://publications.waset.org/pdf/10666
	%V 54
	%X When a small H/W IP is designed, we can develop an
appropriate verification environment by observing the simulated
signal waves, or using the serial test vectors for the fixed output. In the
case of design and verification of a massive parallel processor with
multiple IPs, it-s difficult to make a verification system with existing
common verification environment, and to verify each partial IP. A
TestDrive verification environment can build easy and reliable
verification system that can produce highly intuitive results by
applying Modelsim and SystemVerilog-s DPI. It shows many
advantages, for example a high-level design of a GPGPU processor
design can be migrate to FPGA board immediately.
	%P 611 - 615