Search results for: CMOS IC design
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 4851

Search results for: CMOS IC design

4731 Delay and Energy Consumption Analysis of Conventional SRAM

Authors: Arash Azizi-Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, Ali Barati

Abstract:

The energy consumption and delay in read/write operation of conventional SRAM is investigated analytically as well as by simulation. Explicit analytical expressions for the energy consumption and delay in read and write operation as a function of device parameters and supply voltage are derived. The expressions are useful in predicting the effect of parameter changes on the energy consumption and speed as well as in optimizing the design of conventional SRAM. HSPICE simulation in standard 0.25μm CMOS technology confirms precision of analytical expressions derived from this paper.

Keywords: Read energy consumption, write energy consumption, read delay, write delay.

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4730 A 3.125Gb/s Clock and Data Recovery Circuit Using 1/4-Rate Technique

Authors: Il-Do Jeong, Hang-Geun Jeong

Abstract:

This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in range without using the reference clock. The proposed CDR was implemented using a 1/4-rate bang-bang type phase detector (PD) and a ring voltage controlled oscillator (VCO). The CDR circuit has been fabricated in a standard 0.18 CMOS technology. It occupies an active area of 1 x 1 and consumes 90 mW from a single 1.8V supply.

Keywords: Clock and data recovery, 1/4-rate frequency detector, 1/4-rate phase detector.

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4729 Low Jitter ADPLL based Clock Generator for High Speed SoC Applications

Authors: Moorthi S., Meganathan D., Janarthanan D., Praveen Kumar P., J. Raja paul perinbam

Abstract:

An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps at 100MHz. Since the digitally controlled oscillator (DCO) can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for System-on-Chip (SoC) applications.

Keywords: All Digital Phase Locked Loop (ADPLL), Systemon-Chip (SoC), Phase Locked Loop (PLL), Very High speedIntegrated Circuit (VHSIC) Hardware Description Language(VHDL), Digitally Controlled Oscillator (DCO), Phase frequencydetector (PFD) and Voltage Controlled Oscillator (VCO).

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4728 A 5-V to 30-V Current-Mode Boost Converter with Integrated Current Sensor and Power-on Protection

Authors: Jun Yu, Yat-Hei Lam, Boris Grinberg, Kevin Chai Tshun Chuan

Abstract:

This paper presents a 5-V to 30-V current-mode boost converter for powering the drive circuit of a micro-electro-mechanical sensor. The design of a transconductance amplifier and an integrated current sensing circuit are presented. In addition, essential building blocks for power-on protection such as a soft-start and clamp block and supply and clock ready block are discussed in details. The chip is fabricated in a 0.18-μm CMOS process. Measurement results show that the soft-start and clamp block can effectively limit the inrush current during startup and protect the boost converter from startup failure.

Keywords: Boost Converter, Current Sensing, Power-on protection, Step-up Converter, Soft-start.

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4727 Parametric Optimization of Hospital Design

Authors: M. K. Holst, P. H. Kirkegaard, L. D. Christoffersen

Abstract:

Present paper presents a parametric performancebased design model for optimizing hospital design. The design model operates with geometric input parameters defining the functional requirements of the hospital and input parameters in terms of performance objectives defining the design requirements and preferences of the hospital with respect to performances. The design model takes point of departure in the hospital functionalities as a set of defined parameters and rules describing the design requirements and preferences.

Keywords: Architectural Layout Design, Hospital Design, Parametric design, Performance-based models.

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4726 A Set Theory Based Factoring Technique and Its Use for Low Power Logic Design

Authors: Padmanabhan Balasubramanian, Ryuta Arisaka

Abstract:

Factoring Boolean functions is one of the basic operations in algorithmic logic synthesis. A novel algebraic factorization heuristic for single-output combinatorial logic functions is presented in this paper and is developed based on the set theory paradigm. The impact of factoring is analyzed mainly from a low power design perspective for standard cell based digital designs in this paper. The physical implementation of a number of MCNC/IWLS combinational benchmark functions and sub-functions are compared before and after factoring, based on a simple technology mapping procedure utilizing only standard gate primitives (readily available as standard cells in a technology library) and not cells corresponding to optimized complex logic. The power results were obtained at the gate-level by means of an industry-standard power analysis tool from Synopsys, targeting a 130nm (0.13μm) UMC CMOS library, for the typical case. The wire-loads were inserted automatically and the simulations were performed with maximum input activity. The gate-level simulations demonstrate the advantage of the proposed factoring technique in comparison with other existing methods from a low power perspective, for arbitrary examples. Though the benchmarks experimentation reports mixed results, the mean savings in total power and dynamic power for the factored solution over a non-factored solution were 6.11% and 5.85% respectively. In terms of leakage power, the average savings for the factored forms was significant to the tune of 23.48%. The factored solution is expected to better its non-factored counterpart in terms of the power-delay product as it is well-known that factoring, in general, yields a delay-efficient multi-level solution.

Keywords: Factorization, Set theory, Logic function, Standardcell based design, Low power.

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4725 A Study on Roles of the Community Design in Crime Prevention: Focusing on Project called Root out Crime by Design in South Korea

Authors: Miyoun Won, Youngkyung Choi

Abstract:

In the meantime, there were lots of hardware solutions like products or urban facilities for crime prevention in the public design area. Meanwhile, people have growing interest in public design so by making a village; community design in public design is getting active by the society. The system for crime prevention is actively done by the citizens who created the community. Regarding the social situation, in this project, we saw it as a kind of community design practices and researched about 'how does community design influence Crime prevention?' The purpose of this study is to propose the community design as a way of preventing the crime in the city. First, we found out about the definition, elements and methods of community design by reviewing the theory. And then, this study analyzed the case that was enforced in Seoul and organize the elements and methods of community design. This study can be refer to Public Design based on civil participation and make the community design area contribute to expand the way of solving social problems.

Keywords: Public Design, Sustainable Community Design, Crime Prevention, Participatory Design.

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4724 Highly Optimized Novel High Speed Low Power Barrel Shifter at 22nm Hi K Metal Gate Strained Si Technology Node

Authors: Shobha Sharma, Amita Dev

Abstract:

This research paper presents highly optimized barrel shifter at 22nm Hi K metal gate strained Si technology node. This barrel shifter is having a unique combination of static and dynamic body bias which gives lowest power delay product. This power delay product is compared with the same circuit at same technology node with static forward biasing at ‘supply/2’ and also with normal reverse substrate biasing and still found to be the lowest. The power delay product of this barrel sifter is .39362X10-17J and is lowered by approximately 78% to reference proposed barrel shifter at 32nm bulk CMOS technology. Power delay product of barrel shifter at 22nm Hi K Metal gate technology with normal reverse substrate bias is 2.97186933X10-17J and can be compared with this design’s PDP of .39362X10-17J. This design uses both static and dynamic substrate biasing and also has approximately 96% lower power delay product compared to only forward body biased at half of supply voltage. The NMOS model used are predictive technology models of Arizona state university and the simulations to be carried out using HSPICE simulator.

Keywords: Dynamic body biasing, highly optimized barrel shifter, PDP, Static body biasing.

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4723 Vertical GAA Silicon Nanowire Transistor with Impact of Temperature on Device Parameters

Authors: N. Shen, Z. X. Chen, K.D. Buddharaju, H. M. Chua, X. Li, N. Singh, G.Q Lo, D.-L. Kwong

Abstract:

In this paper, we present a vertical wire NMOS device fabricated using CMOS compatible processes. The impact of temperature on various device parameters is investigated in view of usual increase in surrounding temperature with device density.

Keywords: Gate-all-around, temperature dependence, silicon nanowire

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4722 High-Efficiency Comparator for Low-Power Application

Authors: M. Yousefi, N. Nasirzadeh

Abstract:

In this paper, dynamic comparator structure employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters have been presented. The proposed comparator has low consumption thanks to power reduction methods. They have the ability for offset adjustment. The comparator consumes 14.3 μW at 100 MHz which is equal to 11.8 fJ. The comparator has been designed and simulated in 180 nm CMOS. Layouts occupy 210 μm2.

Keywords: Comparator, low, power, efficiency.

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4721 A Study on using N-Pattern Chains of Design Patterns based on Software Quality Metrics

Authors: Niloofar Khedri, Masoud Rahgozar, MahmoudReza Hashemi

Abstract:

Design patterns describe good solutions to common and reoccurring problems in program design. Applying design patterns in software design and implementation have significant effects on software quality metrics such as flexibility, usability, reusability, scalability and robustness. There is no standard rule for using design patterns. There are some situations that a pattern is applied for a specific problem and this pattern uses another pattern. In this paper, we study the effect of using chain of patterns on software quality metrics.

Keywords: Design Patterns, Design patterns' Relationship, Software quality Metrics, Software Engineering.

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4720 Emulation Model in Architectural Education

Authors: Ö. Şenyiğit, A. Çolak

Abstract:

It is of great importance for an architectural student to know the parameters through which he/she can conduct his/her design and makes his/her design effective in architectural education. Therefore; an empirical application study was carried out through the designing activity using the emulation model to support the design and design approaches of architectural students. During the investigation period, studies were done on the basic design elements and principles of the fall semester, and the emulation model, one of the designing methods that constitute the subject of the study, was fictionalized as three phased “recognition-interpretation-application”. As a result of the study, it was observed that when students were given a key method during the design process, their awareness increased and their aspects improved as well.

Keywords: Basic design, design education, design methods, emulation.

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4719 On the Application of Meta-Design Techniques in Hardware Design Domain

Authors: R. Damaševičius

Abstract:

System-level design based on high-level abstractions is becoming increasingly important in hardware and embedded system design. This paper analyzes meta-design techniques oriented at developing meta-programs and meta-models for well-understood domains. Meta-design techniques include meta-programming and meta-modeling. At the programming level of design process, metadesign means developing generic components that are usable in a wider context of application than original domain components. At the modeling level, meta-design means developing design patterns that describe general solutions to the common recurring design problems, and meta-models that describe the relationship between different types of design models and abstractions. The paper describes and evaluates the implementation of meta-design in hardware design domain using object-oriented and meta-programming techniques. The presented ideas are illustrated with a case study.

Keywords: Design patterns, meta-design, meta-modeling, metaprogramming.

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4718 Single Event Transient Tolerance Analysis in 8051 Microprocessor Using Scan Chain

Authors: Jun Sung Go, Jong Kang Park, Jong Tae Kim

Abstract:

As semi-conductor manufacturing technology evolves; the single event transient problem becomes more significant issue. Single event transient has a critical impact on both combinational and sequential logic circuits, so it is important to evaluate the soft error tolerance of the circuits at the design stage. In this paper, we present a soft error detecting simulation using scan chain. The simulation model generates a single event transient randomly in the circuit, and detects the soft error during the execution of the test patterns. We verified this model by inserting a scan chain in an 8051 microprocessor using 65 nm CMOS technology. While the test patterns generated by ATPG program are passing through the scan chain, we insert a single event transient and detect the number of soft errors per sub-module. The experiments show that the soft error rates per cell area of the SFR module is 277% larger than other modules.

Keywords: Scan chain, single event transient, soft error, 8051 processor.

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4717 Factors of Successful Wooden Furniture Design Process

Authors: S. Choodoung, U. Smutkupt

Abstract:

This study systemizes processes and methods in wooden furniture design that contains uniqueness in function and aesthetics. The study was done by research and analysis for designer-s consideration factors that affect function and production. Therefore, the study result indicates that such factors are design process (planning for design, product specifications, concept design, product architecture, industrial design, production), design evaluation as well as wooden furniture design dependent factors i.e. art (art style; furniture history, form), functionality (the strength and durability, area place, using), material (appropriate to function, wood mechanical properties), joints, cost, safety, and social responsibility. Specifically, all aforementioned factors affect good design. Resulting from direct experience gained through user-s usage, the designer must design the wooden furniture systemically and effectively. As a result, this study selected dinning armchair as a case study with all involving factors and all design process stated in this study.

Keywords: Furniture Design, Function Design, Aesthetic, Wooden Furniture.

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4716 Universal Current-Mode OTA-C KHN Biquad

Authors: Dalibor Biolek, Viera Biolková, Zden─øk Kolka

Abstract:

A universal current-mode biquad is described which represents an economical variant of well-known KHN (Kerwin, Huelsman, Newcomb) voltage-mode filter. The circuit consists of two multiple-output OTAs and of two grounded capacitors. Utilizing simple splitter of the input current and a pair of jumpers, all the basic 2nd-order transfer functions can be implemented. The principle is verified by Spice simulation on the level of a CMOS structure of OTAs.

Keywords: Biquad, current mode, OTA.

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4715 A Study on Creation of Human-Based Co-Design Service Platform

Authors: Chiung-Hui Chen

Abstract:

With the approaching of digital era, various interactive service platforms and systems support human beings- needs in lives by different contents and measures. Design strategies have gradually turned from function-based to user-oriented, and are often customized. In other words, how designers include users- value reaction in creation becomes the goal. Creative design service of interior design requires positive interaction and communication to allow users to obtain full design information, recognize the style and process of personal needs, develop creative service design, lower communication time and cost and satisfy users- sense of achievement. Thus, by constructing a co-design method, based on the communication between interior designers and users, this study recognizes users- real needs and provides the measure of co-design for designers and users.

Keywords: Co-Design, Customized, Design Service, Interactive Genetic Algorithm, Interior Design.

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4714 On the Characteristics of Liquid Explosive Dispersing Flow

Authors: Lei Li, Xiaobing Ren, Xiaoxia Lu, Xiaofang Yan

Abstract:

In this paper, some experiments of liquid dispersion flow driven by explosion in vertical plane were carried out using a liquid explosive dispersion device with film cylindrical constraints. The separated time series describing the breakup shape and dispersion process of liquid were recorded with high speed CMOS camera. The experimental results were analyzed and some essential characteristics of liquid dispersing flow are presented.

Keywords: Explosive Disseminations, liquid dispersion Flow, Cavitations, Gasification.

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4713 Design Management Applications to Improve Work Environment for Female Academics in Saudi Arabia

Authors: Nouf Saad Alnassar, Susan Grant, Ray Holland

Abstract:

This research study examines cases of Saudi Arabian universities and female academics for work environment issues within the context of design management applications. The study proposes use of design research, ergonomics and systems design thinking to develop the university design which facilitates removal of physical and cognitive barriers for female academics. Review of literature demonstrates that macro and micro ergonomic combined with design management and system design strategies can significantly improve the workplace design for female academics. The university design model would be prepared based on the analyses of primary data obtained from archived documents, participants' observation logs, photo audits, focus groups and semi-structured interviews of currently employed female academics in the selected case universities.

Keywords: Design management, workplace design, university design, ergonomics.

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4712 Leakage Reduction ONOFIC Approach for Deep Submicron VLSI Circuits Design

Authors: Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj

Abstract:

Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.

Keywords: Deep submicron, Leakage Current, LECTOR, ONOFIC, Power Delay Product

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4711 An Analysis of Uncoupled Designs in Chicken Egg

Authors: Pratap Sriram Sundar, Chandan Chowdhury, Sagar Kamarthi

Abstract:

Nature has perfected her designs over 3.5 billion years of evolution. Research fields such as biomimicry, biomimetics, bionics, bio-inspired computing, and nature-inspired designs have explored nature-made artifacts and systems to understand nature’s mechanisms and intelligence. Learning from nature, the researchers have generated sustainable designs and innovation in a variety of fields such as energy, architecture, agriculture, transportation, communication, and medicine. Axiomatic design offers a method to judge if a design is good. This paper analyzes design aspects of one of the nature’s amazing object: chicken egg. The functional requirements (FRs) of components of the object are tabulated and mapped on to nature-chosen design parameters (DPs). The ‘independence axiom’ of the axiomatic design methodology is applied to analyze couplings and to evaluate if eggs’ design is good (i.e., uncoupled design) or bad (i.e., coupled design). The analysis revealed that eggs design is a good design, i.e., uncoupled design. This approach can be applied to any nature’s artifacts to judge whether their design is a good or a bad. This methodology is valuable for biomimicry studies. This approach can also be a very useful teaching design consideration of biology and bio-inspired innovation.

Keywords: Uncoupled design, axiomatic design, nature design, design evaluation.

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4710 Incorporation of Safety into Design by Safety Cube

Authors: Mohammad Rajabalinejad

Abstract:

Safety is often seen as a requirement or a performance indicator through the design process, and this does not always result in optimally safe products or systems. This paper suggests integrating the best safety practices with the design process to enrich the exploration experience for designers and add extra values for customers. For this purpose, the commonly practiced safety standards and design methods have been reviewed and their common blocks have been merged forming Safety Cube. Safety Cube combines common blocks for design, hazard identification, risk assessment and risk reduction through an integral approach. An example application presents the use of Safety Cube for design of machinery.

Keywords: Safety, safety cube, design, product, system, machinery.

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4709 Possible Futures for Doctoral Research Training in Design

Authors: D. Barron, M. Zeegers

Abstract:

In this paper, we argue that Design research is basic to countries- national productivity and competition agendas at the same time that vagaries of research training presents as one of the barriers faced by Design Higher Degree by Research students in engaging those agendas. We argue that, given industry requirements for research-trained recruits, students have the right to expect that research training will provide the foundations of a successful career on an academic or research pathway or a professional pathway, but that universities have yet to address problems in their provision of research training for Design doctoral students. We suggest that to facilitate this, rigorous research conducted on the provision of Doctoral programs in Design would serve to inform future activities in Design research in productive ways.

Keywords: Design, Doctoral Design Education, Research Training

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4708 Experimental Investigation of Adjacent Hall Structures Parameters

Authors: Ivelina N. Cholakova, Tihomir B. Takov, Radostin Ts. Tsankov, Nicolas Simonne, Slavka S. Tzanova

Abstract:

Adjacent Hall microsensors, comprising a silicon substrate and four contacts, providing simultaneously two supply inputs and two differential outputs, are characterized. The voltage related sensitivity is in the order of 0.11T-1, and a cancellation method for offset compensation is used, achieving residual offset in the micro scale which is also compared to a single Hall plate.

Keywords: Adjacent Hall sensors, offset compensation, voltage related sensitivity, 0.18μm CMOS technology.

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4707 Optimization of Loudspeaker Part Design Parameters by Air Viscosity Damping Effect

Authors: Yue Hu, Xilu Zhao, Takao Yamaguchi, Manabu Sasajima, Yoshio Koike, Akira Hara

Abstract:

This study optimized the design parameters of a cone loudspeaker as an example of high flexibility of the product design. We developed an acoustic analysis software program that considers the impact of damping caused by air viscosity. In sound reproduction, it is difficult to optimize each parameter of the loudspeaker design. To overcome the limitation of the design problem in practice, this study presents an acoustic analysis algorithm to optimize the design parameters of the loudspeaker. The material character of cone paper and the loudspeaker edge were the design parameters, and the vibration displacement of the cone paper was the objective function. The results of the analysis showed that the design had high accuracy as compared to the predicted value. These results suggested that although the parameter design is difficult, with experience and intuition, the design can be performed easily using the optimized design found with the acoustic analysis software.

Keywords: Air viscosity, design parameters, loudspeaker, optimization.

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4706 Design of a Constant Chord Single-Rotating Propeller using Lock and Goldstein Techniques

Authors: Samrand Rashahmadi, Morteza Abbaszadeh, Sana Hoseyni, Raziyeh Alizadeh

Abstract:

Design of a constant chord propeller is presented in this paper in order to reduce propeller-s design procedure-s costs. The design process was based on Lock and Goldstein-s techniques of propeller design and analysis. In order to calculate optimum chord of propeller, chord of a referential element is generalized as whole blades chord. The design outcome which named CS-X-1 is modeled & analyzed by CFD methods using K-ε: R.N.G turbulence model. Convergence of results of two codes proved that outcome results of design process are reliable. Design result is a two-blade propeller with a total diameter of 1.1 meter, radial velocity of 3000 R.P.M, efficiency above .75 and power coefficient near 1.05.

Keywords: Single rotating propeller, Design, C.F.D. test, constant chord

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4705 Instructional Design and Development Utilizing Technology: A Student Perspective

Authors: Lisa M. Weltzer-Ward, Abbie Brown

Abstract:

The sequence Analyze, Design, Develop, Implement, and Evaluate (ADDIE) provides a powerful methodology for designing computer-based educational materials. Helping students to understand this design process sequence may be achieved by providing them with direct, guided experience. This article examines such help and guidance and the overall learning process from a student-s personal experience.

Keywords: ADDIE, education, instructional design, web design.

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4704 Heat Exchanger Design

Authors: Su Thet Mon Than, Khin Aung Lin, Mi Sandar Mon

Abstract:

This paper is intended to assist anyone with some general technical experience, but perhaps limited specific knowledge of heat transfer equipment. A characteristic of heat exchanger design is the procedure of specifying a design, heat transfer area and pressure drops and checking whether the assumed design satisfies all requirements or not. The purpose of this paper is how to design the oil cooler (heat exchanger) especially for shell-and-tube heat exchanger which is the majority type of liquid-to-liquid heat exchanger. General design considerations and design procedure are also illustrated in this paper and a flow diagram is provided as an aid of design procedure. In design calculation, the MatLAB and AutoCAD software are used. Fundamental heat transfer concepts and complex relationships involved in such exchanger are also presented in this paper. The primary aim of this design is to obtain a high heat transfer rate without exceeding the allowable pressure drop. This computer program is highly useful to design the shell-and-tube type heat exchanger and to modify existing deign.

Keywords: Shell-and-Tube Heat Exchanger, MatLAB and AutoCAD

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4703 Applying Transformative Service Design to Develop Brand Community Service in Women, Children and Infants Retailing

Authors: Shian Wan, Yi-Chang Wang, Yu-Chien Lin

Abstract:

This research discussed the various theories of service design, the importance of service design methodology, and the development of transformative service design framework. In this study, transformative service design is applied while building a new brand community service for women, children and infants retailing business. The goal is to enhance the brand recognition and customer loyalty, effectively increase the brand community engagement by embedding the brand community in social network and ultimately, strengthen the impact and the value of the company brand.

Keywords: Service design, transformative service design, brand community.

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4702 A Novel Design Approach for Mechatronic Systems Based On Multidisciplinary Design Optimization

Authors: Didier Casner, Jean Renaud, Remy Houssin, Dominique Knittel

Abstract:

In this paper, a novel approach for the multidisciplinary design optimization (MDO) of complex mechatronic systems. This approach, which is a part of a global project aiming to include the MDO aspect inside an innovative design process. As a first step, the paper considers the MDO as a redesign approach which is limited to the parametric optimization. After defining and introducing the different keywords, the proposed method which is based on the V-Model which is commonly used in mechatronics.

Keywords: mechatronics, Multidisciplinary Design Optimization (MDO), multiobjective optimization, engineering design.

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