Search results for: Arithmetic Circuits.
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 317

Search results for: Arithmetic Circuits.

137 Research on Simulation Model of Collision Force between Floating Ice and Pier

Authors: Tianlai Yu, Zhengguo Yuan, Sidi Shan

Abstract:

Adopting the measured constitutive relationship of stress-strain of river ice, the finite element analysis model of percussive force of river ice and pier is established, by the explicit dynamical analysis software package LS-DYNA. Effects of element types, contact method and arithmetic of ice and pier, coupled modes between different elements, mesh density of pier, and ice sheet in contact area on the collision force are studied. Some of measures for the collision force analysis of river ice and pier are proposed as follows: bridge girder can adopt beam161 element with 3-node; pier below the line of 1.30m above ice surface and ice sheet use solid164 element with 8-node; in order to accomplish the connection of different elements, the rigid body with 0.01-0.05m thickness is defined between solid164 and beam161; the contact type of ice and pier adopts AUTOMATIC_SURFACE_TO_SURFACE, using symmetrical penalty function algorithms; meshing size of pier below the line of 1.30m above ice surface should not less than 0.25×0.25×0.5m3. The simulation results have the advantage of high precision by making a comparison between measured and computed data. The research results can be referred for collision force study between river ice and pier.

Keywords: River ice, collision force, simulation analysis, ANSYS/LS-DYNA

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136 Bias Stability of a-IGZO TFT and a new Shift-Register Design Suitable for a-IGZO TFT

Authors: Young Wook Lee, Sun-Jae Kim, Soo-Yeon Lee, Moon-Kyu Song, Woo-Geun Lee Min-Koo Han

Abstract:

We have fabricated a-IGZO TFT and investigated the stability under positive DC and AC bias stress. The threshold voltage of a-IGZO TFT shifts positively under those biases, and that reduces on-current. For this reason, conventional shift-register circuit employing TFTs which stressed by positive bias will be unstable, may do not work properly. We have designed a new 6-transistor shift-register, which has less transistors than prior circuits. The TFTs of the proposed shift-register are not suffering from positive DC or AC stress, mainly kept unbiased. Despite the compact design, the stable output signal was verified through the SPICE simulation even under RC delay of clock signal.

Keywords: Indium Gallium Zinc Oxide (IGZO), Thin FilmTransistor (TFT), shift-register

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135 Identification of States and Events for the Static and Dynamic Simulation of Single Electron Tunneling Circuits

Authors: Sharief F. Babiker, Abdelkareem Bedri, Rania Naeem

Abstract:

The implementation of single-electron tunneling (SET) simulators based on the master-equation (ME) formalism requires the efficient and accurate identification of an exhaustive list of active states and related tunnel events. Dynamic simulations also require the control of the emerging states and guarantee the safe elimination of decaying states. This paper describes algorithms for use in the stationary and dynamic control of the lists of active states and events. The paper presents results obtained using these algorithms with different SET structures.

Keywords: Active state, Coulomb blockade, Master Equation, Single electron devices

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134 A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem

Authors: T. Vigneswaran, B. Mukundhan, P. Subbarami Reddy

Abstract:

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.

Keywords: Arithmetic circuit, full adder, multiplier, low power, very Large-scale integration (VLSI).

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133 Using Neural Network for Execution of Programmed Pulse Width Modulation (PPWM) Method

Authors: M. Tarafdar Haque, A. Taheri

Abstract:

Application of neural networks in execution of programmed pulse width modulation (PPWM) of a voltage source inverter (VSI) is studied in this paper. Using the proposed method it is possible to cancel out the desired harmonics in output of VSI in addition to control the magnitude of fundamental harmonic, contineously. By checking the non-trained values and a performance index, the most appropriate neural network is proposed. It is shown that neural networks may solve the custom difficulties of practical utilization of PPWM such as large size of memory, complex digital circuits and controlling the magnitude of output voltage in a discrete manner.

Keywords: Neural Network, Inverter, PPWM.

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132 Algorithmic Method for Efficient Cruise Program

Authors: Pelaez Verdet, Antonio, Loscertales Sanchez, Pilar

Abstract:

One of the mayor problems of programming a cruise circuit is to decide which destinations to include and which don-t. Thus a decision problem emerges, that might be solved using a linear and goal programming approach. The problem becomes more complex if several boats in the fleet must be programmed in a limited schedule, trying their capacity matches best a seasonal demand and also attempting to minimize the operation costs. Moreover, the programmer of the company should consider the time of the passenger as a limited asset, and would like to maximize its usage. The aim of this work is to design a method in which, using linear and goal programming techniques, a model to design circuits for the cruise company decision maker can achieve an optimal solution within the fleet schedule.

Keywords: Itinerary design, cruise programming, goalprogramming, linear programming

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131 Extraction of Semantic Digital Signatures from MRI Photos for Image-Identification Purposes

Authors: Marios Poulos, George Bokos

Abstract:

This paper makes an attempt to solve the problem of searching and retrieving of similar MRI photos via Internet services using morphological features which are sourced via the original image. This study is aiming to be considered as an additional tool of searching and retrieve methods. Until now the main way of the searching mechanism is based on the syntactic way using keywords. The technique it proposes aims to serve the new requirements of libraries. One of these is the development of computational tools for the control and preservation of the intellectual property of digital objects, and especially of digital images. For this purpose, this paper proposes the use of a serial number extracted by using a previously tested semantic properties method. This method, with its center being the multi-layers of a set of arithmetic points, assures the following two properties: the uniqueness of the final extracted number and the semantic dependence of this number on the image used as the method-s input. The major advantage of this method is that it can control the authentication of a published image or its partial modification to a reliable degree. Also, it acquires the better of the known Hash functions that the digital signature schemes use and produces alphanumeric strings for cases of authentication checking, and the degree of similarity between an unknown image and an original image.

Keywords: Computational Geometry, MRI photos, Image processing, pattern Recognition.

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130 Electrical Energy Harvesting Using Thermo Electric Generator for Rural Communities in India

Authors: N. Nandan A. M. Nagaraj, L. Sanjeev Kumar

Abstract:

In the rapidly growing population, the requirement of electrical power is increasing day by day. In order to meet the needs, we need to generate the power using alternate method. In this paper, a presentable approach is developed by analysis and can be implemented by utilizing heat energy, which is generated in numerous ways in some of the rural areas in India. The thermoelectric generator unit will be developed by combing with control circuits and converts, which is used to light the LED lamps. The temperature difference which is available in the kitchens, especially the exhaust pipes/chimneys of wooden fire stoves, where more heat is dissipated into the atmosphere, can be utilized for electrical power generation. Hence, the temperature rise of surroundings atmosphere can be reduced.

Keywords: Thermoelectric generator, LED, converts, temperature.

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129 An Evaluation of Sag Detection Techniques for Fast Solid-State Electronic Transferring to Alternate Electrical Energy Sources

Authors: M. N. Moschakis, I. G. Andritsos, V. V. Dafopoulos, J. M. Prousalidis, E. S. Karapidakis

Abstract:

This paper deals with the evaluation of different detection strategies used in power electronic devices as a critical element for an effective mitigation of voltage disturbances. The effectiveness of those detection schemes in the mitigation of disturbances such as voltage sags by a Solid-State Transfer Switch is evaluated through simulations. All critical parameters affecting their performance is analytically described and presented. Moreover, the effect of fast detection of sags on the overall performance of STS is analyzed and investigated.

Keywords: Faults (short-circuits), industrial engineering, power electronics, power quality, static transfer switch, voltage sags (or dips).

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128 The Effects of Applying Linguistic Principles and Teaching Techniques in Teaching English at Secondary School in Thailand

Authors: Wannakarn Likitrattanaporn

Abstract:

The ultimate purpose of this investigation was to determine the teachers’ opinions as well as students’ opinions towards the Adapted English Lessons. The subjects of the study were 5 Thai teachers, who teach English, and 85 Grade 10 mixed-ability students at Triamudom Suksa Pattanakarn Ratchada School, Bangkok, Thailand. The research instruments included questionnaires and the informal interview. The data from the research instruments was collected and analyzed concerning linguistic principles of minimal pair and articulatory phonetics as well as teaching techniques of mimicry-memorization; vocabulary substitution drills, language pattern drills, reading comprehension exercise, practicing listening, speaking and writing skill and communicative activities; informal talk and free writing. The data was statistically compiled according to an arithmetic percentage. The results showed that the teachers and students have very highly positive opinions towards adapting linguistic principles for teaching and learning phonological accuracy. Teaching techniques provided in the Adapted English Lessons can be used efficiently in the classroom. The teachers and students have positive opinions towards them too.

Keywords: Applying linguistic principles and teaching techniques, teachers’ and students’ opinions, teaching English, the Adapted English Lessons.

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127 The Effect of the Parameters of the Grinding on the Characteristics of the Deposit Phosphate Ore of Kef Es Sennoun, Djebel Onk-Tebessa, Algeria

Authors: N. Benabdeslam, N. Bouzidi, F. Atmani, R. Boucif, A. Sakhri

Abstract:

The objective of this study was to provide answers for a better understanding of the mechanisms involved during grinding. To obtain a phosphate powder, we carry out sieving - grinding circuits for each parameter influencing the process. The analysis of the average particle size of the different tests carried out served in the first place as a basis for the determination of the granulometric curve area, the characteristics and the granular coefficients, then the exploitation of the different results for the calculation of the energies consumed for the fragmentation of different ore types, the energy coefficients as well as the ability to grind. Indeed, a time of 5 to 10 minutes can be chosen as the optimal grinding time in a disc mill for a % in weight of the highest pass. However, grinding time can influence the granular characteristics of ore.

Keywords: Energy, granular characteristics, grinding, mineralogical composition, phosphate ore.

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126 Study of Fast Etching of Silicon for the Fabrication of Bulk Micromachined MEMS Structures

Authors: V. Swarnalatha, A. V. Narasimha Rao, P. Pal

Abstract:

The present research reports the investigation of fast etching of silicon for the fabrication of microelectromechanical systems (MEMS) structures using silicon wet bulk micromachining. Low concentration tetramethyl-ammonium hydroxide (TMAH) and hydroxylamine (NH2OH) are used as main etchant and additive, respectively. The concentration of NH2OH is varied to optimize the composition to achieve best etching characteristics such as high etch rate, significantly high undercutting at convex corner for the fast release of the microstructures from the substrate, and improved etched surface morphology. These etching characteristics are studied on Si{100} and Si{110} wafers as they are most widely used in the fabrication of MEMS structures as wells diode, transistors and integrated circuits.

Keywords: KOH, MEMS, micromachining, silicon, TMAH, wet anisotropic etching.

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125 Control Strategy of SRM Converters for Power Quality Improvement

Authors: Yogesh Pahariya, Rakesh Saxena, Biswaroop Sarkar

Abstract:

The selection of control strategy depends on the converters of the drive including power, speed, performance and the possible system costs. A number of attempts were therefore made in recent times to develop novel power electronic converter structures for SRM drives, based on the utilization. Many of the converters with variable speed drives have no input power factor correction circuits. This results in harmonic pollution of the utility supply, which should be avoided. The effect of power factor variation in terms of harmonic content is also analyzed in this study. The proposed topologies were simulated using MATLAB / Simulink software package and the results are obtained.

Keywords: Harmonic Pollution, Power Electronic Converter, Power Quality, Simulation.

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124 A Novel Approach of Multilevel Inverter with Reduced Power Electronics Devices

Authors: M. Jagabar Sathik, K. Ramani

Abstract:

In this paper family of multilevel inverter topology with reduced number of power switches is presented. The proposed inverter can generate both even and odd level. The proposed topology is suitable for symmetric structure. The proposed symmetric inverter results in reduction of power switches, power diode and gate driver circuits and also it may further minimize the installation area and cost. To prove the superiority of proposed topology is compared with conventional topologies. The performance of this symmetric multilevel inverter has been tested by computer based simulation and prototype based experimental setup for nine-level inverter is developed and results are verified.

Keywords: Cascaded H- Bridge (CHB), Multilevel Inverter (MLI), Nearest Level Modulation (NLM), Total Harmonic Distortion (THD).

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123 Artificial Voltage-Controlled Capacitance and Inductance using Voltage-Controlled Transconductance

Authors: Mansour I. Abbadi, Abdel-Rahman M. Jaradat

Abstract:

In this paper, a technique is proposed to implement an artificial voltage-controlled capacitance or inductance which can replace the well-known varactor diode in many applications. The technique is based on injecting the current of a voltage-controlled current source onto a fixed capacitor or inductor. Then, by controlling the transconductance of the current source by an external bias voltage, a voltage-controlled capacitive or inductive reactance is obtained. The proposed voltage-controlled reactance devices can be designed to work anywhere in the frequency spectrum. Practical circuits for the proposed voltage-controlled reactances are suggested and simulated.

Keywords: voltage-controlled capacitance, voltage-controlled inductance, varactor diode, variable transconductance.

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122 Reducing Power in Error Correcting Code using Genetic Algorithm

Authors: Heesung Lee, Joonkyung Sung, Euntai Kim

Abstract:

This paper proposes a method which reduces power consumption in single-error correcting, double error-detecting checker circuits that perform memory error correction code. Power is minimized with little or no impact on area and delay, using the degrees of freedom in selecting the parity check matrix of the error correcting codes. The genetic algorithm is employed to solve the non linear power optimization problem. The method is applied to two commonly used SEC-DED codes: standard Hamming and odd column weight Hsiao codes. Experiments were performed to show the performance of the proposed method.

Keywords: Error correcting codes, genetic algorithm, non-linearpower optimization, Hamming code, Hsiao code.

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121 Investigation of Chaotic Behavior in DC-DC Converters

Authors: Sajid Iqbal, Masood Ahmed, Suhail Aftab Qureshi

Abstract:

DC-DC converters are widely used in regulated switched mode power supplies and in DC motor drive applications. There are several sources of unwanted nonlinearity in practical power converters. In addition, their operation is characterized by switching that gives birth to a variety of nonlinear dynamics. DC-DC buck and boost converters controlled by pulse-width modulation (PWM) have been simulated. The voltage waveforms and attractors obtained from the circuit simulation have been studied. With the onset of instability, the phenomenon of subharmonic oscillations, quasi-periodicity, bifurcations, and chaos have been observed. This paper is mainly motivated by potential contributions of chaos theory in the design, analysis and control of power converters, in particular and power electronics circuits, in general.

Keywords: Buck converter, boost converter, period- doubling, chaos, bifurcation, strange attractor.

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120 A Finite Precision Block Floating Point Treatment to Direct Form, Cascaded and Parallel FIR Digital Filters

Authors: Abhijit Mitra

Abstract:

This paper proposes an efficient finite precision block floating point (BFP) treatment to the fixed coefficient finite impulse response (FIR) digital filter. The treatment includes effective implementation of all the three forms of the conventional FIR filters, namely, direct form, cascaded and par- allel, and a roundoff error analysis of them in the BFP format. An effective block formatting algorithm together with an adaptive scaling factor is pro- posed to make the realizations more simple from hardware view point. To this end, a generic relation between the tap weight vector length and the input block length is deduced. The implementation scheme also emphasises on a simple block exponent update technique to prevent overflow even during the block to block transition phase. The roundoff noise is also investigated along the analogous lines, taking into consideration these implementational issues. The simulation results show that the BFP roundoff errors depend on the sig- nal level almost in the same way as floating point roundoff noise, resulting in approximately constant signal to noise ratio over a relatively large dynamic range.

Keywords: Finite impulse response digital filters, Cascade structure, Parallel structure, Block floating point arithmetic, Roundoff error.

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119 Highly Scalable, Reversible and Embedded Image Compression System

Authors: Federico Pérez González, Iñaki Goiricelaia Ordorika, Pedro Iriondo Bengoa

Abstract:

A new method for low complexity image coding is presented, that permits different settings and great scalability in the generation of the final bit stream. This coding presents a continuoustone still image compression system that groups loss and lossless compression making use of finite arithmetic reversible transforms. Both transformation in the space of color and wavelet transformation are reversible. The transformed coefficients are coded by means of a coding system in depending on a subdivision into smaller components (CFDS) similar to the bit importance codification. The subcomponents so obtained are reordered by means of a highly configure alignment system depending on the application that makes possible the re-configure of the elements of the image and obtaining different levels of importance from which the bit stream will be generated. The subcomponents of each level of importance are coded using a variable length entropy coding system (VBLm) that permits the generation of an embedded bit stream. This bit stream supposes itself a bit stream that codes a compressed still image. However, the use of a packing system on the bit stream after the VBLm allows the realization of a final highly scalable bit stream from a basic image level and one or several enhance levels.

Keywords: Image compression, wavelet transform, highlyscalable, reversible transform, embedded, subcomponents.

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118 Electrical Properties of n-CdO/p-Si Heterojunction Diode Fabricated by Sol Gel

Authors: S.Aksoy, Y.Caglar

Abstract:

n-CdO/p-Si heterojunction diode was fabricated using sol-gel spin coating technique which is a low cost and easily scalable method for preparing of semiconductor films. The structural and morphological properties of CdO film were investigated. The X-ray diffraction (XRD) spectra indicated that the film was of polycrystalline nature. The scanning electron microscopy (SEM) images indicate that the surface morphology CdO film consists of the clusters formed with the coming together of the nanoparticles. The electrical characterization of Au/n-CdO/p–Si/Al heterojunction diode was investigated by current-voltage. The ideality factor of the diode was found to be 3.02 for room temperature. The reverse current of the diode strongly increased with illumination intensity of 100 mWcm-2 and the diode gave a maximum open circuit voltage Voc of 0.04 V and short-circuits current Isc of 9.92×10-9 A.

Keywords: CdO, heterojunction semiconductor devices, ideality factor, current-voltage characteristics

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117 Internal Node Stabilization for Voltage Sense Amplifiers in Multi-Channel Systems

Authors: Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn

Abstract:

This paper discusses the undesirable charge transfer by the parasitic capacitances of the input transistors in a voltage sense amplifier. Due to its intrinsic rail-to-rail voltage transition, the input sides are inevitably disturbed. It can possible disturb the stabilities of the reference voltage levels. Moreover, it becomes serious in multi-channel systems by altering them for other channels, and so degrades the linearity of the systems. In order to alleviate the internal node voltage transition, the internal node stabilization technique is proposed by utilizing an additional biasing circuit. It achieves 47% and 43% improvements for node stabilization and input referred disturbance, respectively.

Keywords: Voltage sense amplifier, voltage transition, node stabilization, and biasing circuits.

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116 On-Chip Aging Sensor Circuit Based on Phase Locked Loop Circuit

Authors: Ararat Khachatryan, Davit Mirzoyan

Abstract:

In sub micrometer technology, the aging phenomenon starts to have a significant impact on the reliability of integrated circuits by bringing performance degradation. For that reason, it is important to have a capability to evaluate the aging effects accurately. This paper presents an accurate aging measurement approach based on phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuit. The architecture is rejecting the circuit self-aging effect from the characteristics of PLL, which is generating the frequency without any aging phenomena affects. The aging monitor is implemented in low power 32 nm CMOS technology, and occupies a pretty small area. Aging simulation results show that the proposed aging measurement circuit improves accuracy by about 2.8% at high temperature and 19.6% at high voltage.

Keywords: Nanoscale, aging, effect, NBTI, HCI.

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115 Modelling of Induction Motor Including Skew Effect Using MWFA for Performance Improvement

Authors: M. Harir, A. Bendiabdellah, A. Chaouch, N. Benouzza

Abstract:

This paper deals with the modelling and simulation of the squirrel cage induction motor by taking into account all space harmonic components as well as the introduction of the bars skew in the calculation of the linear evolution of the magnetomotive force (MMF) between the slots extremities. The model used is based on multiple coupled circuits and the modified winding function approach (MWFA). The effect of skewing is included in the calculation of motors inductances with an axial asymmetry in the rotor. The simulation results in both time and spectral domains show the effectiveness and merits of the model and the error that may be caused if the skew of the bars are neglected.

Keywords: Modelling, MWFA, Skew effect, Squirrel cage induction motor, Spectral domain.

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114 130 nm CMOS Mixer and VCO for 2.4 GHz Low-power Wireless Personal Area Networks

Authors: Gianluca Cornetta, David J. Santos

Abstract:

This paper describes a 2.4 GHz passive switch mixer and a 5/2.5 GHz voltage-controlled negative Gm oscillator (VCO) with an inversion-mode MOS varactor. Both circuits are implemented using a 1P8M 0.13 μm process. The switch mixer has an input referred 1 dB compression point of -3.89 dBm and a conversion gain of -0.96 dB when the local oscillator power is +2.5 dBm. The VCO consumes only 1.75 mW, while drawing 1.45 mA from a 1.2 V supply voltage. In order to reduce the passives size, the VCO natural oscillation frequency is 5 GHz. A clocked CMOS divideby- two circuit is used for frequency division and quadrature phase generation. The VCO has a -109 dBc/Hz phase noise at 1 MHz frequency offset and a 2.35-2.5 GHz tuning range (after the frequency division), thus complying with ZigBee requirements.

Keywords: Switch Mixers, Varactors, IEEE 802.15.4 (ZigBee), Direct Conversion Receiver, Wireless Sensor Networks.

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113 Increasing Directional Intensity of Output Light Beam from Photonic Crystal Slab Outlet Including Micro Cavity Resonators

Authors: A. Mobini, K. Saghafi, V. Ahmadi

Abstract:

in this paper we modified a simple two-dimensional photonic crystal waveguide by creating micro cavity resonators in order to increase the output light emission which can be applicable to photonic integrated circuits. The micro cavity resonators are constructed by removing two tubes close to the waveguide output. Coupling emitted light from waveguide with those micro cavities, results increasing intensity of waveguide output light. Inserting a tube in last row of waveguide, we have improved directionality of output light beam.

Keywords: photonic crystal, waveguide, micro cavity resonators, directional emission

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112 Reversible, Embedded and Highly Scalable Image Compression System

Authors: Federico Pérez González, Iñaki Goirizelaia Ordorika, Pedro Iriondo Bengoa

Abstract:

In this work a new method for low complexity image coding is presented, that permits different settings and great scalability in the generation of the final bit stream. This coding presents a continuous-tone still image compression system that groups loss and lossless compression making use of finite arithmetic reversible transforms. Both transformation in the space of color and wavelet transformation are reversible. The transformed coefficients are coded by means of a coding system in depending on a subdivision into smaller components (CFDS) similar to the bit importance codification. The subcomponents so obtained are reordered by means of a highly configure alignment system depending on the application that makes possible the re-configure of the elements of the image and obtaining different importance levels from which the bit stream will be generated. The subcomponents of each importance level are coded using a variable length entropy coding system (VBLm) that permits the generation of an embedded bit stream. This bit stream supposes itself a bit stream that codes a compressed still image. However, the use of a packing system on the bit stream after the VBLm allows the realization of a final highly scalable bit stream from a basic image level and one or several improvement levels.

Keywords: Image compression, wavelet transform, highly scalable, reversible transform, embedded, subcomponents.

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111 Implementation of Quantum Rotation Gates Using Controlled Non-Adiabatic Evolutions

Authors: Abdelrahman A. H. Abdelrahim, Gharib Subhi Mahmoud, Sherzod Turaev, Azeddine Messikh

Abstract:

Quantum gates are the basic building blocks in the quantum circuits model. These gates can be implemented using adiabatic or non adiabatic processes. Adiabatic models can be controlled using auxiliary qubits, whereas non adiabatic models can be simplified by using one single-shot implementation. In this paper, the controlled adiabatic evolutions is combined with the single-shot implementation to obtain quantum gates with controlled non adiabatic evolutions. This is an important improvement which can speed the implementation of quantum gates and reduce the errors due to the long run in the adiabatic model. The robustness of our scheme to different types of errors is also investigated.

Keywords: Adiabatic evolutions, non adiabatic evolutions, controlled adiabatic evolutions, quantum rotation gates, dephasing rates, master equation.

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110 An Optimization Tool-Based Design Strategy Applied to Divide-by-2 Circuits with Unbalanced Loads

Authors: Agord M. Pinto Jr., Yuzo Iano, Leandro T. Manera, Raphael R. N. Souza

Abstract:

This paper describes an optimization tool-based design strategy for a Current Mode Logic CML divide-by-2 circuit. Representing a building block for output frequency generation in a RFID protocol based-frequency synthesizer, the circuit was designed to minimize the power consumption for driving of multiple loads with unbalancing (at transceiver level). Implemented with XFAB XC08 180 nm technology, the circuit was optimized through MunEDA WiCkeD tool at Cadence Virtuoso Analog Design Environment ADE.

Keywords: Divide-by-2 circuit, CMOS technology, PLL phase locked-loop, optimization tool, CML current mode logic, RF transceiver.

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109 Stabilization Technique for Multi-Inputs Voltage Sense Amplifiers in Node Sharing Converters

Authors: Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn

Abstract:

This paper discusses the undesirable charge transfer through the parasitic capacitances of the input transistors in a multi-inputs voltage sense amplifier. Its intrinsic rail-to-rail voltage transitions at the output nodes inevitably disturb the input sides through the capacitive coupling between the outputs and inputs. Then, it can possible degrade the stabilities of the reference voltage levels. Moreover, it becomes more serious in multi-channel systems by altering them for other channels, and so degrades the linearity of the overall systems. In order to alleviate the internal node voltage transition, the internal node stabilization techniques are proposed. It achieves 45% and 40% improvements for node stabilization and input referred disturbance, respectively.

Keywords: Voltage sense amplifier, multi-inputs, voltage transition, node stabilization, and biasing circuits.

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108 Potential of Tourism Logistic Service Business in the Border Areas of Chong Anma, Chong Sa-Ngam, and Chong Jom Checkpoints in Thailand to Increase Competitive Efficiency among the ASEAN Community

Authors: Pariwat Somnuek

Abstract:

This study focused on tourism logistic services in the border areas of Thailand by an analysis and comparison of the opinions of tourists, villagers, and entrepreneurs of these services. Sample representatives of this study were a total of 600 villagers and 15 entrepreneurs in the three border areas consisting of Chong Anma, Chong Sa-Ngam, and Chong Jom checkpoints. For methodology, survey questionnaires, situation analysis, TOWS matrix, and focus group discussions were used for data collection, as well as descriptive analysis and statistics such as arithmetic means and standard deviations, were employed for data analysis. The findings revealed that business potential was at the medium level and entrepreneurs were satisfied with their turnovers. However, perspectives of transportation and tourism services provided for tourists need to be immediately improved. Recommendations for the potential development included promotion of border tourism destinations and foreign investments into accommodation, restaurants, and transport, as well as the establishment of business networks between Thailand and Cambodia, along with the introduction of new tourism destinations by co-operation between entrepreneurs in both countries. These initiatives may lead to increased visitors, collaboration of security offices, and an improved image of tourism security.

Keywords: Business potential, potential development, tourism logistics, services.

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