Internal Node Stabilization for Voltage Sense Amplifiers in Multi-Channel Systems
This paper discusses the undesirable charge transfer by the parasitic capacitances of the input transistors in a voltage sense amplifier. Due to its intrinsic rail-to-rail voltage transition, the input sides are inevitably disturbed. It can possible disturb the stabilities of the reference voltage levels. Moreover, it becomes serious in multi-channel systems by altering them for other channels, and so degrades the linearity of the systems. In order to alleviate the internal node voltage transition, the internal node stabilization technique is proposed by utilizing an additional biasing circuit. It achieves 47% and 43% improvements for node stabilization and input referred disturbance, respectively.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1337101Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2390
 A. Cabrini, R. Micheloni, O, Khouri, S. Gregori, and G. Torelli, "High input range sense comparator for multilevel flash memories,” in Proceedings of the 2004 Int. Symp. Circuits and Systems, May 2004, pp. 657-660.
 G. R. Chaji and A. Nathan, "A current-mode comparator for digital calibration of amorphous silicon AMOLED displays,” IEEETran. Circuits and Systems-II: Express Briefs, vol. 55, no. 7, pp. 614-618, July, 2008.
 Seyed Danesh, Jed Hurwitz, Keith Findlater, David Renshaw, and Robert Henderson, "A reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit highly time-interleaved counter ADC with low power comparator design,” IEEE J. Solid-State Circuits, vol. 48, no. 3, pp. 733-748, Mar., 2013.
 DanielSchinkel,EisseMensink, Eric A.M. Klumperink, Ed (A. J. M.) van Tuijl, and Bram Nauta,"A 3Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects,” IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 297-306, Jan., 2006.
 BorivojeNikolic, Vojin G. Oklobdzija, Vladimir Stojanovic, WenyanJia, James K. Chiu, and Michael M. Leung, "Improved sense-amplifier-based flop-flop: design and measurements,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876-884, June, 2000.
 K.-L. J. Wong and C.-K. K. Yang, "Offset compensation in comparators with minimum input-referred supply noise,” IEEE J. Solid-State Circuits, pp. 837-840, vol. 39, no. 5, May, 2004.
 DanielSchinkel, EisseMensink, Eric Klumperink, Ed van Tuijl and Bram Nauta, "A double-tail latch-type voltage sense amplifier with 18ps setup+hold time,” in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conference, Feb. 2007, pp. 314-605.
 Y. Wang and B. Razavi, "An 8-bit 150-MHz CMOS A/D converter,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 308-317, Mar. 2000.
 Lalitkumar Y. Nathawad, RyoheiUrata, Bruce A. Wooley, and David A. B. Miller, "A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2021-2030, Dec. 2000.
 N. S. Sooch, "MOS cascode current mirror,” U.S. Patent 4,550,284, Oct/ 1985.
 P. R. Gray, P. J. Hurst, S. H. Lewis, R. G. Meyer, Analog and Design of Analog Integrated Circuits,4th ed., John Wiley & Sons, Inc., 2001.