Commenced in January 2007
Paper Count: 31100
130 nm CMOS Mixer and VCO for 2.4 GHz Low-power Wireless Personal Area Networks
Abstract:This paper describes a 2.4 GHz passive switch mixer and a 5/2.5 GHz voltage-controlled negative Gm oscillator (VCO) with an inversion-mode MOS varactor. Both circuits are implemented using a 1P8M 0.13 μm process. The switch mixer has an input referred 1 dB compression point of -3.89 dBm and a conversion gain of -0.96 dB when the local oscillator power is +2.5 dBm. The VCO consumes only 1.75 mW, while drawing 1.45 mA from a 1.2 V supply voltage. In order to reduce the passives size, the VCO natural oscillation frequency is 5 GHz. A clocked CMOS divideby- two circuit is used for frequency division and quadrature phase generation. The VCO has a -109 dBc/Hz phase noise at 1 MHz frequency offset and a 2.35-2.5 GHz tuning range (after the frequency division), thus complying with ZigBee requirements.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1076736Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1851
 Seo H-M., Moon, Y., Park, Y-K., Kim, D., Kim, D-S., Lee, Y-S., Won, K-H., Kim, S-D., and Choi, P.,A Low-Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks, IEEE Trans. on VLSI Systems, v. 15, n. 2, February 2007, pp.227-231.
 Timarm, A., Vamos, A., and Bognar, G.,Comprehensive design of a high frequency PLL synthesizer for ZigBee application, 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and systems, Prague, Czech Republic, April 18-21, 2006, pp. 37-41
 Darabi, H., and Abidi, A. A.Noise in RF-CMOS Mixers: A Simple Physical Model, IEEE Jour. of Solid State Circuits, Vol. 35, n. 1, January 2004, pp. 15-25.
 Shahani, A. R., Shaeffer, D. K., and Lee, T. H. A 12 mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver, IEEE Jour. of Solid State Circuits, Vol. 39, n. 6, June 2004, pp. 952-955.
 Bernstein, K., Carrig, K. M., Durham, C. M., Hansen, P. R., Hogenmiller, D., Nowak, E. J., and Rohrer, N. J.High Speed CMOS Design Styles, Dordrecht, The Netherlands: Kluwer Academic Publishers, 1998.
 Caverly, R.,CMOS RFIC Design Principles, Boston, MA: Artech House, 2007.
 Razavi, B.,RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.
 Chi, B., and Shi, B. Low-power CMOS and its Divide-by-two Dividers with Quadrature Outputs for 5 GHz/2.5 GHz WLAN Transceivers, IEEE Conference on Communication Circuits and Systems, June 2002, pp. 57- 60.
 Plouchart, J-O., Ainspan, H., Soyner, M., and Ruehli, A. A Fully- Monotlithic SiGe Differential Voltage-Controlled Oscillator for 5 GHz Wireless Applications, IEEE Symp. on Radio Frequency Integrated Circuits, June 2000, pp. 57-60.
 Kim, H-R., Cha, C-Y., Oh, S-M., Yang, M-S., and Lee, S-G. A Very Low-Power Quadrature VCO with Back-Gate Coupling, IEEE Jour. of Solid State Circuits, Vol. 39, n. 6, June 2004, pp. 952-955.
 Tsai, Y-C., Shen, Y-S., and Jou, C. F. A Low-Power Quadrature VCO Using Current-reused Technique and Back-Gate Coupling, PIERS Online, Vol. 3, n. 7, July 2007, pp. 952-955.
 Gil, J., Kwon, I., and Shin, H. CMOS Implementation of a 2.4-GHz Switch Mixer and Quadrature VCO, Jour. of the Korean Physical Society, Vol. 42, n. 3, February 2003, pp. 241-245.