Search results for: lower bound of processor elements

Authors: I. Otete, A. I. Ejere, I. S. Okunzuwa

Abstract:

In this work, we used the Hulthen-Yukawa potential to obtain the bound state energy eigenvalues of the Schrödinger equation in D-dimensions within the frame work of the Nikiforov-Uvarov (NU) method. We demonstrated the graphical behaviour of the Hulthen and the Yukawa potential and investigated how the screening parameter and the potential depth affected the structure and the nature of the bound state eigenvalues. The results we obtained showed that increasing the screening parameter lowers the energy eigenvalues. Also, the eigenvalues acted as an inverse function of the potential depth. That is, increasing the potential depth reduces the energy eigenvalues.

Keywords: Schrödinger's equation, bound state, Hulthen-Yukawa potential, Nikiforov-Uvarov, D-dimensions

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Authors: Toshitaka Higashino, Naoki Wakamiya

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Human beings perform a task by perceiving information from outside, recognizing them, and responding them. There have been various attempts to analyze and understand internal processes behind the reaction to a given stimulus by conducting psychological experiments and analysis from multiple perspectives. Among these, we focused on Model Human Processor (MHP). However, it was built based on psychological experiments and thus the relation with brain activity was unclear so far. To verify the validity of the MHP and propose our model from a viewpoint of neuroscience, EEG (Electroencephalography) measurements are performed during experiments in this study. More specifically, first, experiments were conducted where Latin alphabet characters were used as visual stimuli. In addition to response time, ERPs (event-related potentials) such as N100 and P300 were measured by using EEG. By comparing cycle time predicted by the MHP and latency of ERPs, it was found that N100, related to perception of stimuli, appeared at the end of the perceptual processor. Furthermore, by conducting an additional experiment, it was revealed that P300, related to decision making, appeared during the response decision process, not at the end. Second, by experiments using Japanese Hiragana characters, i.e. Japan's own phonetic symbols, those findings were confirmed. Finally, Japanese Kanji characters were used as more complicated visual stimuli. A Kanji character usually has several readings and several meanings. Despite the difference, a reading-related task and a meaning-related task exhibited similar results, meaning that they involved similar information processing processes of the brain. Based on those results, our model was proposed which reflects response time and ERP latency. It consists of three processors: the perception processor from an input of a stimulus to appearance of N100, the cognitive processor from N100 to P300, and the decision-action processor from P300 to response. Using our model, an application system which reflects brain activity can be established.

Keywords: Brain activity, EEG, information processing model, model human processor.

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Authors: Lina Wu, Jia Liu, Ye Li

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The goal of this project is to investigate constant properties (called the Liouville-type Problem) for a p-stable map as a local or global minimum of a p-energy functional where the domain is a Euclidean space and the target space is a closed half-ellipsoid. The First and Second Variation Formulas for a p-energy functional has been applied in the Calculus Variation Method as computation techniques. Stokes’ Theorem, Cauchy-Schwarz Inequality, Hardy-Sobolev type Inequalities, and the Bochner Formula as estimation techniques have been used to estimate the lower bound and the upper bound of the derived p-Harmonic Stability Inequality. One challenging point in this project is to construct a family of variation maps such that the images of variation maps must be guaranteed in a closed half-ellipsoid. The other challenging point is to find a contradiction between the lower bound and the upper bound in an analysis of p-Harmonic Stability Inequality when a p-energy minimizing map is not constant. Therefore, the possibility of a non-constant p-energy minimizing map has been ruled out and the constant property for a p-energy minimizing map has been obtained. Our research finding is to explore the constant property for a p-stable map from a Euclidean space into a closed half-ellipsoid in a certain range of p. The certain range of p is determined by the dimension values of a Euclidean space (the domain) and an ellipsoid (the target space). The certain range of p is also bounded by the curvature values on an ellipsoid (that is, the ratio of the longest axis to the shortest axis). Regarding Liouville-type results for a p-stable map, our research finding on an ellipsoid is a generalization of mathematicians’ results on a sphere. Our result is also an extension of mathematicians’ Liouville-type results from a special ellipsoid with only one parameter to any ellipsoid with (n+1) parameters in the general setting.

Keywords: Bochner Formula, Stokes’ Theorem, Cauchy-Schwarz Inequality, first and second variation formulas, Hardy-Sobolev type inequalities, Liouville-type problem, p-harmonic map.

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Authors: Udaya Kumar Reddy K. R, K. Viswanathan Iyer

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Given a simple connected unweighted undirected graph G = (V (G), E(G)) with |V (G)| = n and |E(G)| = m, we present a new algorithm for the all-pairs shortest-path (APSP) problem. The running time of our algorithm is in O(n2 log n). This bound is an improvement over previous best known O(n2.376) time bound of Raimund Seidel (1995) for general graphs. The algorithm presented does not rely on fast matrix multiplication. Our algorithm with slight modifications, enables us to compute the APSP problem for unweighted directed graph in time O(n2 log n), improving a previous best known O(n2.575) time bound of Uri Zwick (2002).

Keywords: Distance in graphs, Dynamic programming, Graphalgorithms, Shortest paths.

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Authors: Baoguang Tian, Nan Chen

Abstract:

A new relative efficiency in linear model in reference is instructed into the linear weighted regression, and its upper and lower bound are proposed. In the linear weighted regression model, for the best linear unbiased estimation of mean matrix respect to the least-squares estimation, two new relative efficiencies are given, and their upper and lower bounds are also studied.

Keywords: Linear weighted regression, Relative efficiency, Mean matrix, Trace.

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Authors: Sudhakara G, Hemanth Kumar A.R

Abstract:

In this paper, we define distance partition of vertex set of a graph G with reference to a vertex in it and with the help of the same, a graph with metric dimension two (i.e. β (G) = 2 ) is characterized. In the process, we develop a polynomial time algorithm that verifies if the metric dimension of a given graph G is two. The same algorithm explores all metric bases of graph G whenever β (G) = 2 . We also find a bound for cardinality of any distance partite set with reference to a given vertex, when ever β (G) = 2 . Also, in a graph G with β (G) = 2 , a bound for cardinality of any distance partite set as well as a bound for number of vertices in any sub graph H of G is obtained in terms of diam H .

Keywords: Metric basis, Distance partition, Metric dimension.

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Authors: Ionel Zagan, Vasile Gheorghita Gaitan

Abstract:

The development of CPUs and of real-time systems based on them made it possible to use time at increasingly low resolutions. Together with the scheduling methods and algorithms, time organizing has been improved so as to respond positively to the need for optimization and to the way in which the CPU is used. This presentation contains both a detailed theoretical description and the results obtained from research on improving the performances of the nMPRA (Multi Pipeline Register Architecture) processor by implementing specific functions in hardware. The proposed CPU architecture has been developed, simulated and validated by using the FPGA Virtex-7 circuit, via a SoC project. Although the nMPRA processor hardware structure with five pipeline stages is very complex, the present paper presents and analyzes the tests dedicated to the implementation of the CPU and of the memory on-chip for instructions and data. In order to practically implement and test the entire SoC project, various tests have been performed. These tests have been performed in order to verify the drivers for peripherals and the boot module named Bootloader.

Keywords: Hardware scheduler, nMPRA processor, real-time systems, scheduling methods.

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Authors: Dilek Nartop, Nurşen Sarı, Hatice Öğütçü

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Novel polystrene-bound Schiff bases and their Pt(IV) complexes have been prepared from condensation reaction of polystyrene-A-NH2 with 2-hydroxybenzaldehyde and 5-fluoro-3- bromo-2-hydroxybenzaldehyde. The structures of Pt(IV) complexes with polystyrene including Schiff bases have been determined by elemental analyses, magnetic susceptibility, IR, 1H-NMR, UV-vis, TG/DTA and AAS. The antibacterial and antifungal activities of the synthesized compounds have been studied by the well-diffusion method against some selected microorganisms: (Bacillus cereus spp., Listeria monocytogenes 4b, Micrococcus luteus, Staphylococcus aureus, Staphylococcus epidermis, Brucella abortus, Escherichia coli, Pseudomonas putida spp., Shigella dysenteria type 10, Salmonella typhi H).

Keywords: Polymer-bound Schiff bases, polystyrene-A-NH2, Pt(IV) complexes, biological activity.

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Authors: Yukinari Minagi , Akinori Kanasugi

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This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operation. The proposed arithmetic circuit performs floating-point arithmetic which is frequently used in science and technology. The data format is floating-point based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

Keywords: dynamic reconfiguration, floating-point arithmetic, double precision, FPGA

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Authors: Marie Mikušová, Petr Šnapka, Viktorie Janečková

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As every system conceptions the concept of crisis is based on the system of interdependent elements. These dialectic elements occur in a majority of definitions even though called differently. For further theoretical searching but also for practical utilization it is necessary to understand these elements. The paper stresses that the concept of crisis is ambiguous. There are identified and explained the elements that are generally found in most crises (disruption, precondition, triggers etc).

Keywords: Concept, crisis, element

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Authors: Ahmed Madian, Muaz Aljarhi

Abstract:

Coordinate Rotation Digital Computer (CORDIC) is a unique digital computing unit intended for the computation of mathematical operations and functions. This paper presents A multi CORDIC processor that integrates different CORDIC architectures on a single FPGA chip and allows the user to select the CORDIC architecture to proceed with based on what he wants to calculate and his needs. Synthesis show that radix 2 CORDIC has the lowest clock delay, radix 8 CORDIC has the highest LUT usage and lowest register usage while Hybrid Radix 4 CORDIC had the highest clock delay.

Keywords: Multi, CORDIC, FPGA, Processor.

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Authors: Hamed Homaei, Iraj Mahdavi, Ali Tajdin

Abstract:

One of the main concerns of miners is to increase the quality level of their products because the mining metals price depends on their quality level; however, increasing the quality level of these products has different costs at different levels of the supply chain. These costs usually increase after extractor level. This paper studies the coordination issue of a decentralized three-level supply chain with one supplier (extractor), one mineral processor and one manufacturer in which the increasing product quality level cost at the processor level is higher than the supplier and at the level of the manufacturer is more than the processor. We identify the optimal product quality level for each supply chain member by designing a revenue sharing contract. Finally, numerical examples show that the designed contract not only increases the final product quality level but also provides a win-win condition for all supply chain members and increases the whole supply chain profit.

Keywords: Three-stage supply chain, product quality improvement, channel coordination, revenue sharing.

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Authors: Kwang Y. Lee, Tae R. Park, Jae C. Kwak, Yong S. Koo

Abstract:

When a small H/W IP is designed, we can develop an appropriate verification environment by observing the simulated signal waves, or using the serial test vectors for the fixed output. In the case of design and verification of a massive parallel processor with multiple IPs, it-s difficult to make a verification system with existing common verification environment, and to verify each partial IP. A TestDrive verification environment can build easy and reliable verification system that can produce highly intuitive results by applying Modelsim and SystemVerilog-s DPI. It shows many advantages, for example a high-level design of a GPGPU processor design can be migrate to FPGA board immediately.

Keywords: Virtual Simulation, Verification, IP Design, GPGPU

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Authors: Emilija Miletic, Milos Krstic, Maxim Piz, Michael Methfessel

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In this work we present a solution for DAGC (Digital Automatic Gain Control) in WLAN receivers compatible to IEEE 802.11a/g standard. Those standards define communication in 5/2.4 GHz band using Orthogonal Frequency Division Multiplexing OFDM modulation scheme. WLAN Transceiver that we have used enables gain control over Low Noise Amplifier (LNA) and a Variable Gain Amplifier (VGA). The control over those signals is performed in our digital baseband processor using dedicated hardware block DAGC. DAGC in this process is used to automatically control the VGA and LNA in order to achieve better signal-to-noise ratio, decrease FER (Frame Error Rate) and hold the average power of the baseband signal close to the desired set point. DAGC function in baseband processor is done in few steps: measuring power levels of baseband samples of an RF signal,accumulating the differences between the measured power level and actual gain setting, adjusting a gain factor of the accumulation, and applying the adjusted gain factor the baseband values. Based on the measurement results of RSSI signal dependence to input power we have concluded that this digital AGC can be implemented applying the simple linearization of the RSSI. This solution is very simple but also effective and reduces complexity and power consumption of the DAGC. This DAGC is implemented and tested both in FPGA and in ASIC as a part of our WLAN baseband processor. Finally, we have integrated this circuit in a compact WLAN PCMCIA board based on MAC and baseband ASIC chips designed from us.

Keywords: WLAN, AGC, RSSI, baseband processor

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Authors: Anju S. Pillai, T.B. Isha

Abstract:

With the necessity of increased processing capacity with less energy consumption; power aware multiprocessor system has gained more attention in the recent future. One of the additional challenges that is to be solved in a multi-processor system when compared to uni-processor system is job allocation. This paper presents a novel task dependent job allocation algorithm: Energy centric- Allocation (Ec-A) and Rate Monotonic (RM) scheduling to minimize energy consumption in a multiprocessor system. A simulation analysis is carried out to verify the performance increase with reduction in energy consumption and required number of processors in the system.

Keywords: Energy consumption, Job allocation, Multiprocessor systems, Task dependent.

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Authors: Rameswar Debnath, Haruhisa Takahashi

Abstract:

An evolutionary method whose selection and recombination operations are based on generalization error-bounds of support vector machine (SVM) can select a subset of potentially informative genes for SVM classifier very efficiently [7]. In this paper, we will use the derivative of error-bound (first-order criteria) to select and recombine gene features in the evolutionary process, and compare the performance of the derivative of error-bound with the error-bound itself (zero-order) in the evolutionary process. We also investigate several error-bounds and their derivatives to compare the performance, and find the best criteria for gene selection and classification. We use 7 cancer-related human gene expression datasets to evaluate the performance of the zero-order and first-order criteria of error-bounds. Though both criteria have the same strategy in theoretically, experimental results demonstrate the best criterion for microarray gene expression data.

Keywords: support vector machine, generalization error-bound, feature selection, evolutionary algorithm, microarray data

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Authors: Iman Zangeneh, Mostafa Moradi, Mazyar Baranpouyan

Abstract:

System is using multiple processors for computing and information processing, is increasing rapidly speed operation of these systems compared with single processor systems, very significant impact on system performance is increased .important differences to yield a single multi-processor cpu, the scheduling policies, to reduce the implementation time of all processes. Notwithstanding the famous algorithms such as SPT, LPT, LSPT and RLPT for scheduling and there, but none led to the answer are not optimal.In this paper scheduling using genetic algorithms and innovative way to finish the whole process faster that we do and the result compared with three algorithms we mentioned.

Keywords: Multiprocessor system, genetic algorithms, time implementation process.

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Authors: Niveditha Domse, Kris Kumar, K. N. Balasubramanya Murthy

Abstract:

The more recent satellite projects/programs makes extensive usage of real – time embedded systems. 16 bit processors which meet the Mil-Std-1750 standard architecture have been used in on-board systems. Most of the Space Applications have been written in ADA. From a futuristic point of view, 32 bit/ 64 bit processors are needed in the area of spacecraft computing and therefore an effort is desirable in the study and survey of 64 bit architectures for space applications. This will also result in significant technology development in terms of VLSI and software tools for ADA (as the legacy code is in ADA). There are several basic requirements for a special processor for this purpose. They include Radiation Hardened (RadHard) devices, very low power dissipation, compatibility with existing operational systems, scalable architectures for higher computational needs, reliability, higher memory and I/O bandwidth, predictability, realtime operating system and manufacturability of such processors. Further on, these may include selection of FPGA devices, selection of EDA tool chains, design flow, partitioning of the design, pin count, performance evaluation, timing analysis etc. This project deals with a brief study of 32 and 64 bit processors readily available in the market and designing/ fabricating a 64 bit RISC processor named RISC MicroProcessor with added functionalities of an extended double precision floating point unit and a 32 bit signal processing unit acting as co-processors. In this paper, we emphasize the ease and importance of using Open Core (OpenSparc T1 Verilog RTL) and Open “Source" EDA tools such as Icarus to develop FPGA based prototypes quickly. Commercial tools such as Xilinx ISE for Synthesis are also used when appropriate.

Keywords: RISC MicroProcessor, RPC – RISC Processor Core, PBX – Processor to Block Interface part of the Interconnection Network, BPX – Block to Processor Interface part of the Interconnection Network, FPU – Floating Point Unit, SPU – Signal Processing Unit, WB – Wishbone Interface, CTU – Clock and Test Unit

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Authors: Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis

Abstract:

Speedups from mapping four real-life DSP applications on an embedded system-on-chip that couples coarsegrained reconfigurable logic with an instruction-set processor are presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elements. A design flow for improving application-s performance is proposed. Critical software parts, called kernels, are accelerated on the Coarse-Grained Reconfigurable Array. The kernels are detected by profiling the source code. For mapping the detected kernels on the reconfigurable logic a prioritybased mapping algorithm has been developed. Two 4x4 array architectures, which differ in their interconnection structure among the Processing Elements, are considered. The experiments for eight different instances of a generic system show that important overall application speedups have been reported for the four applications. The performance improvements range from 1.86 to 3.67, with an average value of 2.53, compared with an all-software execution. These speedups are quite close to the maximum theoretical speedups imposed by Amdahl-s law.

Keywords: Reconfigurable computing, Coarse-grained reconfigurable array, Embedded systems, DSP, Performance

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Authors: Chih-Wei Hsieh, Chau-Yi Chou, Sheng-HsiuKuo, Tsung-Che Tsai, I-Chen Wu

Abstract:

This paper presents the benchmarking results and performance evaluation of differentclustersbuilt atthe National Center for High-Performance Computingin Taiwan. Performance of processor, memory subsystem andinterconnect is a critical factor in the overall performance of high performance computing platforms. The evaluation compares different system architecture and software platforms. Most supercomputer used HPL to benchmark their system performance, in accordance with the requirement of the TOP500 List. In this paper we consider system memory access factors that affect benchmark performance, such as processor and memory performance.We hope these works will provide useful information for future development and construct cluster system.

Keywords: Performance Evaluation, Benchmarking and High-Performance Computing

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Authors: Yun Jong Choi, Nam Woong, PooGyeon Park

Abstract:

Variable Structure Control (VSC) is one of the most useful tools handling the practical system with uncertainties and disturbances. Up to now, unfortunately, not enough studies on the input-saturated system with linear-growth-bound disturbances via VSC have been presented. Therefore, this paper proposes an asymp¬totic stability condition for the system via VSC. The designed VSC controller consists of two control parts. The linear control part plays a role in stabilizing the system, and simultaneously, the nonlinear control part in rejecting the linear-growth-bound disturbances perfectly. All conditions derived in this paper are expressed with Linear Matrices Inequalities (LMIs), which can be easily solved with an LMI toolbox in MATLAB.

Keywords: Input saturation, linear-growth bounded disturbances, linear matrix inequality (LMI), variable structure control

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Authors: Megumi Shibuya, Tomohiko Ogishi

Abstract:

Recently, content delivery services have grown rapidly over the Internet. For ASPs (Application Service Provider) providing content delivery services, P2P architecture is beneficial to reduce outgoing traffic from content servers. On the other hand, ISPs are suffering from the increase in P2P traffic. The P2P traffic is unnecessarily redundant because the same content or the same fractions of content are transferred through an inter-ISP link several times. Subscriber ISPs have to pay a transit fee to upstream ISPs based on the volume of inter-ISP traffic. In order to solve such problems, several works have been done for the purpose of P2P traffic reduction. However, these existing works cannot control the traffic volume of a certain link. In order to solve such an ISP-s operational requirement, we propose a method to control traffic volume for a link within a preconfigured upper bound value. We evaluated that the proposed method works well by conducting a simulation on a 1,000-user scale. We confirm that the traffic volume could be controlled at a lower level than the upper bound for all evaluated conditions. Moreover, our method could control the traffic volume at 98.95% link usage against the target value.

Keywords: P2P, traffic control, traffic localization, ALTO.

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Authors: Hwan Su Jung, Ahn Jun Gil, Jong Tae Kim

Abstract:

Power management techniques are necessary to save power in the microprocessor. By changing the frequency and/or operating voltage of processor, DVFS can control power consumption. In this paper, we perform a case study to find optimal power state transition for DVFS. We propose the equation to find the optimal ratio between executions of states while taking into account the deadline of processing time and the power state transition delay overhead. The experiment is performed on the Cortex-M4 processor, and average 6.5% power saving is observed when DVFS is applied under the deadline condition.

Keywords: Deadline, Dynamic Voltage Frequency Scaling, Power State Transition.

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Authors: Shuimiao Wan, Chao Yuan, Baoguang Tian

Abstract:

In statistics parameter theory, usually the parameter estimations have two kinds, one is the least-square estimation (LSE), and the other is the best linear unbiased estimation (BLUE). Due to the determining theorem of minimum variance unbiased estimator (MVUE), the parameter estimation of BLUE in linear model is most ideal. But since the calculations are complicated or the covariance is not given, people are hardly to get the solution. Therefore, people prefer to use LSE rather than BLUE. And this substitution will take some losses. To quantize the losses, many scholars have presented many kinds of different relative efficiencies in different views. For the linear weighted regression model, this paper discusses the relative efficiencies of LSE of β to BLUE of β. It also defines two new relative efficiencies and gives their lower bounds.

Keywords: Linear weighted regression, Relative efficiency, Lower bound, Parameter estimation.

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Authors: Sook-Yeon Shim, Hwan-Su Seo, Tae-Hyun Kim, Hongkyu Kim

Abstract:

The purpose of this study is to identify ideal urban design elements of waterfronts and to analyze the differences in users- cognition among these elements. This study follows three steps as following: first is identifying the urban design elements of waterfronts from literature review and second is evaluating intended users- cognition of urban design elements in urban waterfronts. Lastly, third is analyzing the users- cognition differences. As the result, evaluations of waterfront areas by users show similar features that non-waterfront urban design elements contain the highest degree of importance. This indicates the difference of users- cognition has dimensions of frequency and distance, and demonstrates differences in the aspect of importance than of satisfaction. Multi-Dimensional Scaling Method verifies differences among their cognition. This study provides elements to increase satisfaction of users from differences of their cognition on design elements for waterfronts. It also suggests implications on elements when waterfronts are built.

Keywords: Cognition Difference, , Multi-Dimensional Scaling , Urban Design Elements , Waterfront

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Authors: Sa-aat Niwitpong, Rada Somkhuean, Suparat Niwitpong

Abstract:

This paper presents the generalized p-values for testing the Behrens-Fisher problem when one variance is unknown. We also derive a closed form expression of the upper bound of the proposed generalized p-value.

Keywords: Generalized p-value, hypothesis testing, upper bound.

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Authors: Choon Ki Ahn, Jung Hun Park, Wook Hyun Kwon

Abstract:

CEMTool is a command style design and analyzing package for scientific and technological algorithm and a matrix based computation language. In this paper, we present new 2D & 3D finite element method (FEM) packages for CEMTool. We discuss the detailed structures and the important features of pre-processor, solver, and post-processor of CEMTool 2D & 3D FEM packages. In contrast to the existing MATLAB PDE Toolbox, our proposed FEM packages can deal with the combination of the reserved words. Also, we can control the mesh in a very effective way. With the introduction of new mesh generation algorithm and fast solving technique, our FEM packages can guarantee the shorter computational time than MATLAB PDE Toolbox. Consequently, with our new FEM packages, we can overcome some disadvantages or limitations of the existing MATLAB PDE Toolbox.

Keywords: CEMTool, Finite element method (FEM), Numericalanalysis, Partial differential equation (PDE)

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Authors: Sudipta Majumdar

Abstract:

This paper presents a method for identification of a linear time invariant (LTI) autonomous all pole system using singular value decomposition. The novelty of this paper is two fold: First, MUSIC algorithm for estimating complex frequencies from real measurements is proposed. Secondly, using the proposed algorithm, we can identify the coefficients of differential equation that determines the LTI system by switching off our input signal. For this purpose, we need only to switch off the input, apply our complex MUSIC algorithm and determine the coefficients as symmetric polynomials in the complex frequencies. This method can be applied to unstable system and has higher resolution as compared to time series solution when, noisy data are used. The classical performance bound, Cramer Rao bound (CRB), has been used as a basis for performance comparison of the proposed method for multiple poles estimation in noisy exponential signal.

Keywords: MUSIC algorithm, Cramer Rao bound, frequency estimation.

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Authors: Ezequiel Herruzo, Juan José Cruz, José Ignacio Benavides, Oscar Plata

Abstract:

This paper describes a new algorithm of arrangement in parallel, based on Odd-Even Mergesort, called division and concurrent mixes. The main idea of the algorithm is to achieve that each processor uses a sequential algorithm for ordering a part of the vector, and after that, for making the processors work in pairs in order to mix two of these sections ordered in a greater one, also ordered; after several iterations, the vector will be completely ordered. The paper describes the implementation of the new algorithm on a Message Passing environment (such as MPI). Besides, it compares the obtained experimental results with the quicksort sequential algorithm and with the parallel implementations (also on MPI) of the algorithms quicksort and bitonic sort. The comparison has been realized in an 8 processors cluster under GNU/Linux which is running on a unique PC processor.

Keywords: Parallel algorithm, arrangement, MPI, sorting, parallel program.

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Authors: Kuo-Lung Wu

Abstract:

The weighting exponent m is called the fuzzifier that can have influence on the clustering performance of fuzzy c-means (FCM) and mÎ[1.5,2.5] is suggested by Pal and Bezdek [13]. In this paper, we will discuss the robust properties of FCM and show that the parameter m will have influence on the robustness of FCM. According to our analysis, we find that a large m value will make FCM more robust to noise and outliers. However, if m is larger than the theoretical upper bound proposed by Yu et al. [14], the sample mean will become the unique optimizer. Here, we suggest to implement the FCM algorithm with mÎ[1.5,4] under the restriction when m is smaller than the theoretical upper bound.

Keywords: Fuzzy c-means, robust, fuzzifier.

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