Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 32586
CPU Architecture Based on Static Hardware Scheduler Engine and Multiple Pipeline Registers

Authors: Ionel Zagan, Vasile Gheorghita Gaitan


The development of CPUs and of real-time systems based on them made it possible to use time at increasingly low resolutions. Together with the scheduling methods and algorithms, time organizing has been improved so as to respond positively to the need for optimization and to the way in which the CPU is used. This presentation contains both a detailed theoretical description and the results obtained from research on improving the performances of the nMPRA (Multi Pipeline Register Architecture) processor by implementing specific functions in hardware. The proposed CPU architecture has been developed, simulated and validated by using the FPGA Virtex-7 circuit, via a SoC project. Although the nMPRA processor hardware structure with five pipeline stages is very complex, the present paper presents and analyzes the tests dedicated to the implementation of the CPU and of the memory on-chip for instructions and data. In order to practically implement and test the entire SoC project, various tests have been performed. These tests have been performed in order to verify the drivers for peripherals and the boot module named Bootloader.

Keywords: Hardware scheduler, nMPRA processor, real-time systems, scheduling methods.

Digital Object Identifier (DOI):

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 859


[1] G. C. Buttazzo, “Hard Real-Time Computing Systems - Predictable Scheduling Algorithms and Applications,” Third edition, Springer, 2011, ISBN: 978-1-4614-0675-4.
[2] W. Stallings, “Computer Organization and Architecture,” 10th Edition, 2015, ISBN: 978-0134101613.
[3] E. Dodiu and V. G. Gaitan, “Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers – concept and theory of operation” in IEEE EIT International Conference on Electro-Information Technology, Indianapolis, IN, USA, pp. 1-5, May 2012.
[4] V. G. Gaitan, N. C. Gaitan, and I. Ungurean, “CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1661-1674, Sept. 2015.
[5] J. Shawash, and D. R. Selviah, “Real-time nonlinear parameter estimation using the Levenberg–Marquardt algorithm on field programmable gate arrays,” IEEE Trans. Ind. Electron., vol. 60, no. 1, pp. 170–176, Jan. 2013.
[6] M. Shahbazi, P. Poure, S. Saadate, and M. R. Zolghadri, “Fault-tolerant five-leg converter topology with FPGA-based reconfigurable control,” IEEE Trans. Ind. Electron., vol. 60, no. 6, pp. 2284–2294, Jun. 2013.
[7] T. T. Phuong, K. Ohishi, Y. Yokokura, and C. Mitsantisuk, “FPGA-based high-performance force control system with friction-free and noisefree force observation,” IEEE Trans. Ind. Electron., vol. 61, no. 2, pp. 994–1008, Feb. 2014.
[8] D. A. Patterson and J. L. Hennessy, “Computer Organization and Design, Revised Fourth Edition: The Hardware-Software Interface,” Fourth Edition, 2011, ISBN: 978-0-12-374750-1.
[9] I. Zagan, “Improving the performance of CPU architectures by reducing the Operating System overhead,” in the 3rd IEEE Workshop on Advances in Information, Electronic and Electrical Engineering AIEEE’2015, pp. 1-6, 13-14 Nov. 2015, Riga, Latvia.
[10] “MIPS® Architecture for Programmers Volume I-A: Introduction to the MIPS32® Architecture,” Revision 3.02, Mar. 2011, Available: (Accessed: May 2016).
[11] I. Zagan and V. G. Gaitan, “Schedulability Analysis of nMPRA Processor based on Multithreaded Execution,” in 13rt International Conference on Development and Application Systems, Suceava, Romania, pp. 130-134, May 19-21, 2016.
[12],mips32r1 (Accessed: Sept. 2015).
[13] (Accessed: Aug. 2016).
[14] E. E Moisuc, A. B. Larionescu, and V. G. Gaitan, “Hardware Event Treating in nMPRA,” in 12rt International Conference on Development and Application Systems, Suceava, Romania, pp. 66-69, 15–17 May, 2014.
[15] I. Zagan, “Real-time evaluation of nMPRA CPU Architecture based on Multithreaded Execution,” in 8th International Conference on Computer Science and Information Technology, Amsterdam, Netherlands, 10–11 Dec. 2015.
[16] N. C. Gaitan, I. Zagan, and V. G. Gaitan, “Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation,” International Journal of Advanced Computer Science and Applications – IJACSA, vol. 6, no. 4, 2015.