Search results for: SIW Circuits

Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand, Tan Kong Yew

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This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 Rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics.

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Authors: Yngvar Berg, Mehdi Azadmehr

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In this paper we present a linear autozeroing ultra lowvoltage amplifier. The autozeroing performed by all ULV circuits is important to reduce the impact of noise and especially avoid power supply noise in mixed signal low-voltage CMOS circuits. The simulated data presented is relevant for a 90nm TSMC CMOS process.

Keywords: Low-voltage, trans conductance amplifier, linearity, floating-gate.

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Authors: E. Farshidi

Abstract:

This paper presents a new general technique for analysis of noise in static log-domain translinear circuits. It is demonstrated that employing this technique, leads to a general, simple and routine method of the noise analysis. The circuit has been simulated by HSPICE. The simulation results are seen to conform to the theoretical analysis and shows benefits of the proposed circuit.

Keywords: Noise analysis, log-domain, static, dynamic, translinear loop, companding.

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Authors: Shashank Gautam, Pramod Sharma

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In present era, development of digital circuits, signal processors and other integrated circuits, magnitude comparators are challenged by large area and more power consumption. Comparator is most basic circuit that performs comparison. This paper presents a technique to design a two bit comparator which consumes less area and power. DSCH and MICROWIND version 3 are used to design the schematic and design the layout of the schematic, observe the performance parameters at different nanometer technologies respectively.

Keywords: Chip design, consumed power, layout area, two bit comparator.

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Authors: G.Ramana Murthy, C.Senthilpari, P.Velrajkumar, Lim Tien Sze

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The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other existing six adder circuits in terms of power, propagation delay and PDP. The proposed adder circuit is further analyzed for interconnect analysis, which gives better performance than other adder circuits in terms of layout thickness, width and height.

Keywords: Full Adder, Interconnect Analysis, Low-Power, Multiplexer, Propagation Delay, Parametric Analysis.

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Authors: Yang Luo, Beibei Wang

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In this paper, we present a design methodology of lightweight register transfer level (RTL) hardware threat implemented based on a MAX II FPGA platform. The dynamic power consumed by the toggling of the various bit of registers as well as the dynamic power consumed per unit of logic circuits were analyzed. The hardware threat was designed taking advantage of the differences in dynamic power consumed per unit of logic circuits to hide the transfer information. The experiment result shows that the register hardware threat was successfully implemented by using different dynamic power consumed per unit of logic circuits to hide the key information of DES encryption module. It needs more than 100000 sample curves to reduce the background noise by comparing the sample space when it completely meets the time alignment requirement. In additional, an external trigger signal is playing a very important role to detect the hardware threat in this experiment.

Keywords: Side-channel analysis, hardware threat, register transfer level, dynamic power.

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Authors: Majid Reza Naseh, Mohammad Haeri

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This paper introduces an adaptive control scheme to synchronize two identical Chua's systems. Introductory part of the paper is presented in the first part of the paper and then in the second part, a new theorem is proposed based on which an adaptive control scheme is developed to synchronize two identical modified Chua's circuit. Finally, numerical simulations are included to verify the effectiveness of the proposed control method.

Keywords: Chaos synchronization, adaptive control, Chua's circuits.

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Authors: Wenji Zhu, Yigang He

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This paper presents a new method of analog fault diagnosis based on back-propagation neural networks (BPNNs) using wavelet decomposition and fractal dimension as preprocessors. The proposed method has the capability to detect and identify faulty components in an analog electronic circuit with tolerance by analyzing its impulse response. Using wavelet decomposition to preprocess the impulse response drastically de-noises the inputs to the neural network. The second preprocessing by fractal dimension can extract unique features, which are the fed to a neural network as inputs for further classification. A comparison of our work with [1] and [6], which also employs back-propagation (BP) neural networks, reveals that our system requires a much smaller network and performs significantly better in fault diagnosis of analog circuits due to our proposed preprocessing techniques.

Keywords: Analog circuits, fault diagnosis, tolerance, wavelettransform, fractal dimension, box dimension.

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Authors: Alexandr A. Penin

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Application of projective geometry to the theory of two-ports and cascade circuits with a load change is considered. The equations linking the input and output of a two-port are interpreted as projective transformations which have the invariant as a cross-ratio of four points. This invariant has place for all regime parameters in all parts of a cascade circuit. This approach allows justifying the definition of a regime and its change, to calculate a circuit without explicitly finding the aparameters, to transmit accurately an analogue signal through the unstable two-port.

Keywords: Circuit regime, geometric circuit theory, projective geometry, two-port.

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Authors: Paulo S. Caparelli, Eduardo Costa, Alexsandro S. Soares, Hipolito Barbosa

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This paper presents an evolutionary method for designing electronic circuits and numerical methods associated with monitoring systems. The instruments described here have been used in studies of weather and climate changes due to global warming, and also in medical patient supervision. Genetic Programming systems have been used both for designing circuits and sensors, and also for determining sensor parameters. The authors advance the thesis that the software side of such a system should be written in computer languages with a strong mathematical and logic background in order to prevent software obsolescence, and achieve program correctness.

Keywords: Pattern recognition, evolutionary computation, biological signal, functional programming.

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Authors: Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert

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Evolvable hardware (EHW) refers to a selfreconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). A lot of research has been done in this area several different EA have been introduced. Every time a specific EA is chosen for solving a particular problem, all its components, such as population size, initialization, selection mechanism, mutation rate, and genetic operators, should be selected in order to achieve the best results. In the last three decade a lot of research has been carried out in order to identify the best parameters for the EA-s components for different “test-problems". However different researchers propose different solutions. In this paper the behaviour of mutation rate on (1+λ) evolution strategy (ES) for designing logic circuits, which has not been done before, has been deeply analyzed. The mutation rate for an EHW system modifies values of the logic cell inputs, the cell type (for example from AND to NOR) and the circuit output. The behaviour of the mutation has been analyzed based on the number of generations, genotype redundancy and number of logic gates used for the evolved circuits. The experimental results found provide the behaviour of the mutation rate to be used during evolution for the design and optimization of logic circuits. The researches on the best mutation rate during the last 40 years are also summarized.

Keywords: Evolvable hardware, mutation rate, evolutionarycomputation, design of logic circuit.

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Authors: Zdeňka Dostálová, David Matoušek, Bohumil Brtnik

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As there are also graph methods of circuit analysis in addition to algebraic methods, it is, in theory, clearly possible to carry out an analysis of a whole switched circuit in two-phase switching exclusively by the graph method as well. This article deals with two methods of full-graph solving of switched circuits: by transformation graphs and by two-graphs. It deals with the circuit switched capacitors and the switched current, too. All methods are presented in an equally detailed steps to be able to compare.

Keywords: Switched capacitors of two phases, switched currents of two phases, transformation graph, two-graph, Mason's formula, voltage transfer, summary graph.

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Authors: Jianping Hu, Xiaolei Sheng

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This paper introduces an adiabatic register file based on two-phase CPAL (Complementary Pass-Transistor Adiabatic Logic circuits) with power-gating scheme, which can operate on a single-phase power clock. A 32×32 single-phase adiabatic register file with power-gating scheme has been implemented with TSMC 0.18μm CMOS technology. All the circuits except for the storage cells employ two-phase CPAL circuits, and the storage cell is based on the conventional memory one. The two-phase non-overlap power-clock generator with power-gating scheme is used to supply the proposed adiabatic register file. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. Compared with the traditional static CMOS register file, HSPICE simulations show that the proposed adiabatic register file can work very well, and it attains about 73% energy savings at 100 MHz.

Keywords: Low power, Register file, Complementarypass-transistor logic, Adiabatic logic, Single-phase power clock.

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Authors: Gilberto Gonzalez-A, Dunia Nuñez-P

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Bond graph models of an electrical transformer including the nonlinear saturation are presented. The transformer using electrical and magnetic circuits are modelled. These models determine the relation between self and mutual inductances, and the leakage and magnetizing inductances of power transformers with two windings using the properties of a bond graph. The equivalence between electrical and magnetic variables is given. The modelling and analysis using this methodology to three phase power transformers can be extended.

Keywords: Bond graph, electrical transformer, magnetic circuits, nonlinear saturation.

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Authors: Ebrahim Farshidi

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This paper presents a new circuit arrangement for a current-mode Wheatstone bridge that is suitable for low-voltage integrated circuits implementation. Compared to the other proposed circuits, this circuit features severe reduction of the elements number, low supply voltage (1V) and low power consumption (<350uW). In addition, the circuit has favorable nonlinearity error (<0.35%), operate with multiple sensors and works by single supply voltage. The circuit employs MOSFET transistors, so it can be used for standard CMOS fabrication. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.

Keywords: Wheatstone bridge, current-mode, low-voltage, MOS.

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Authors: D. Krishnaveni, M. Geetha Priya

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Application of reversible logic in integrated circuits results in the improved optimization of power consumption. This technology can be put into use in a variety of low power applications such as quantum computing, optical computing, nano-technology, and Complementary Metal Oxide Semiconductor (CMOS) Very Large Scale Integrated (VLSI) design etc. Logic gates are the basic building blocks in the design of any logic network and thus integrated circuits. In this paper, reversible Dual Key Gate (DKG) and Dual key Gate Pair (DKGP) gates that work singly as full adder/full subtractor are used to realize the basic building blocks of logic circuits. Reversible full adder/subtractor and parallel adder/ subtractor are designed using other reversible gates available in the literature and compared with that of DKG & DKGP gates. Efficient performance of reversible logic circuits relies on the optimization of the key parameters viz number of constant inputs, garbage outputs and number of reversible gates. The full adder/subtractor and parallel adder/subtractor design with reversible DKGP and DKG gates results in least number of constant inputs, garbage outputs, and number of reversible gates compared to the other designs. Thus, this paper provides a threshold to build more complex arithmetic systems using these reversible logic gates, leading to the enhanced performance of computing systems.

Keywords: Low power CMOS, quantum computing, reversible logic gates, full adder, full subtractor, parallel adder/subtractor, basic gates, universal gates.

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Authors: Yavar Safaei Mehrabani, Mehdi Hosseinzadeh

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As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo 2n+1 adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set (2n-1,2n, 2n+1). In this manuscript we have introduced novel binary representation to the design of modulo 2n+1 adder. VLSI realization of proposed architecture under 180 nm full static CMOS technology reveals its superiority in terms of area, power consumption and power-delay product (PDP) against several peer existing structures.

Keywords: Computer arithmetic, modulo 2n+1 adders, Residue Number System (RNS), VLSI.

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Authors: Saeed H. Nasiri, Rahim Faez, Bita Davoodi, Maryam Farrokhi

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Bode stability analysis based on transmission line modeling (TLM) for single wall carbon nanotube (SWCNT) interconnects used in 3D-VLSI circuits is investigated for the first time. In this analysis, the dependence of the degree of relative stability for SWCNT interconnects on the geometry of each tube has been acquired. It is shown that, increasing the length and diameter of each tube, SWCNT interconnects become more stable.

Keywords: Bode stability criterion, Interconnects, Interlayer via, Single wall carbon nanotubes, Transmission line method, Time domain analysis

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Authors: Ali Al-Ataby , Fawzi Al-Naima

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Symbolic Circuit Analysis (SCA) is a technique used to generate the symbolic expression of a network. It has become a well-established technique in circuit analysis and design. The symbolic expression of networks offers excellent way to perform frequency response analysis, sensitivity computation, stability measurements, performance optimization, and fault diagnosis. Many approaches have been proposed in the area of SCA offering different features and capabilities. Numerical Interpolation methods are very common in this context, especially by using the Fast Fourier Transform (FFT). The aim of this paper is to present a method for SCA that depends on the use of Wavelet Transform (WT) as a mathematical tool to generate the symbolic expression for large circuits with minimizing the analysis time by reducing the number of computations.

Keywords: Numerical Interpolation, Sparse Matrices, SymbolicAnalysis, Wavelet Transform.

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Authors: Jerome G. Chandraseelan, Samuel M. D. Oliveira, Antti Häkkinen, Sofia Startceva, Andre S. Ribeiro

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We used live E. coli containing synthetic genetic oscillators to study how the degree of synchrony between the genetic circuits of sister cells changes with temperature. We found that both the mean and the variability of the degree of synchrony between the fluorescence signals from sister cells are affected by temperature. Also, while most pairs of sister cells were found to be highly synchronous in each condition, the number of asynchronous pairs increased with increasing temperature, which was found to be due to disruptions in the oscillations. Finally we provide evidence that these disruptions tend to affect multiple generations as opposed to individual cells. These findings provide insight in how to design more robust synthetic circuits and in how cell division can affect their dynamics.

Keywords: Repressilator, robustness, synchrony, synthetic biology.

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Authors: Sara Felloni, Giuliano Strini

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We explore entanglement in composite quantum systems and how its peculiar properties are exploited in quantum information and communication protocols by means of Diagrams of States, a novel method to graphically represent and analyze how quantum information is elaborated during computations performed by quantum circuits. We present quantum diagrams of states for Bell states generation, measurements and projections, for dense coding and quantum teleportation, for probabilistic quantum machines designed to perform approximate quantum cloning and universal NOT and, finally, for quantum privacy amplification based on entanglement purification. Diagrams of states prove to be a useful approach to analyze quantum computations, by offering an intuitive graphic representation of the processing of quantum information. They also help in conceiving novel quantum computations, from describing the desired information processing to deriving the final implementation by quantum gate arrays.

Keywords: Diagrams of states, entanglement, quantum circuits, quantum information.

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Authors: K. A. Sumithradevi, Vijayalakshmi. M. N., Annamma Abraham., Dr. Vasanta

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The various applications of VLSI circuits in highperformance computing, telecommunications, and consumer electronics has been expanding progressively, and at a very hasty pace. This paper describes a new model for partitioning a circuit using DBSCAN and fuzzy ARTMAP neural network. The first step is concerned with feature extraction, where we had make use DBSCAN algorithm. The second step is the classification and is composed of a fuzzy ARTMAP neural network. The performance of both approaches is compared using benchmark data provided by MCNC standard cell placement benchmark netlists. Analysis of the investigational results proved that the fuzzy ARTMAP with DBSCAN model achieves greater performance then only fuzzy ARTMAP in recognizing sub-circuits with lowest amount of interconnections between them The recognition rate using fuzzy ARTMAP with DBSCAN is 97.7% compared to only fuzzy ARTMAP.

Keywords: VLSI, Circuit partitioning, DBSCAN, fuzzyARTMAP.

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Authors: Jelena Slugan, Ivica Ružić

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We are witnessing the rapid development of technologies that change the world around us. However, curriculums and teaching processes are often slow to adapt to the change; it takes time, money and expertise to implement technology in the classroom. Therefore, the University of Split, Croatia, partnered with local school Marko Marulić High School and created the project "Modern competence in modern high schools" as part of which five different curriculums for STEM areas were developed. One of the curriculums involves combining information technology with physics. The main idea was to teach students how to use different circuits and microcomputers to explore nature and physical phenomena. As a result, using electrical circuits, students are able to recreate in the classroom the phenomena that they observe every day in their environment. So far, high school students had very little opportunity to perform experiments independently, and especially, those physics experiment did not involve ICT. Therefore, this project has a great importance, because the students will finally get a chance to develop themselves in accordance to modern technologies. This paper presents some new methods of teaching physics that will help students to develop experimental skills through the study of deterministic nature of physical laws. Students will learn how to formulate hypotheses, model physical problems using the electronic circuits and evaluate their results. While doing that, they will also acquire useful problem solving skills.

Keywords: ICT in physics, curriculum, laboratory activities, STEM.

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Authors: Padmanabhan Balasubramanian, Bashetty Raghavendra

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In this paper, an analysis is presented, which demonstrates the effect pre-logic factoring could have on an automated combinational logic synthesis process succeeding it. The impact of pre-logic factoring for some arbitrary combinatorial circuits synthesized within a FPGA based logic design environment has been analyzed previously. This paper explores a similar effect, but with the non-regenerative logic synthesized using elements of a commercial standard cell library. On an overall basis, the results obtained pertaining to the analysis on a variety of MCNC/IWLS combinational logic benchmark circuits indicate that pre-logic factoring has the potential to facilitate simultaneous power, delay and area optimized synthesis solutions in many cases.

Keywords: Algebraic factoring, Combinational logic synthesis, Standard cells, Low power, Delay optimization, Area reduction.

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Authors: Jae Young Park, Soongyu Kwon, Kyu Han Kim, Hyeong Geon Lee, Jong Tae Kim

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This paper considers the problem of finding low cost chip set for a minimum cost partitioning of a large logic circuits. Chip sets are selected from a given library. Each chip in the library has a different price, area, and I/O pin. We propose a low cost chip set selection algorithm. Inputs to the algorithm are a netlist and a chip information in the library. Output is a list of chip sets satisfied with area and maximum partitioning number and it is sorted by cost. The algorithm finds the sorted list of chip sets from minimum cost to maximum cost. We used MCNC benchmark circuits for experiments. The experimental results show that all of chip sets found satisfy the multiple partitioning constraints.

Keywords: lowest cost chip set, MCNC benchmark, multi-way partitioning.

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Authors: Labar Hocine, Rekik Badri, Bounaya Kamel, Kelaiaia Mounia Samira

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Diagnostic goal of transformers in service is to detect the winding or the core in fault. Transformers are valuable equipment which makes a major contribution to the supply security of a power system. Consequently, it is of great importance to minimize the frequency and duration of unwanted outages of power transformers. So, Frequency Response Analysis (FRA) is found to be a useful tool for reliable detection of incipient mechanical fault in a transformer, by finding winding or core defects. The authors propose as first part of this article, the coupled circuits method, because, it gives most possible exhaustive modelling of transformers. And as second part of this work, the application of FRA in low frequency in order to improve and simplify the response reading. This study can be useful as a base data for the other transformers of the same categories intended for distribution grid.

Keywords: Diagnostic, Coupled Circuit Method, FRA, Transformer Faults

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Authors: Shiyang Zhu, G. Q. Lo, D. L. Kwong

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Silicon photonics has generated an increasing interest in recent years mainly for optical communications optical interconnects in microelectronic circuits or bio-sensing applications. The development of elementary passive and active components (including detectors and modulators), which are mainly fabricated on the silicon on insulator platform for CMOS-compatible fabrication, has reached such a performance level that the integration challenge of silicon photonics with microelectronic circuits should be addressed. Since crystalline silicon can only be grown from another silicon crystal, making it impossible to deposit in this state, the optical devices are typically limited to a single layer. An alternative approach is to integrate a photonic layer above the CMOS chip using back-end CMOS fabrication process. In this paper, various materials, including silicon nitride, amorphous silicon, and polycrystalline silicon, for this purpose are addressed.

Keywords: Silicon photonics, CMOS, Integration.

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Authors: M. T. Anwar, P. K. Lala, P. Thenappan

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This paper presents the decoder design for the single error correcting and double error detecting code proposed by the authors in an earlier paper. The speed of error detection and correction of a code is largely dependent upon the associated encoder and decoder circuits. The complexity and the speed of such circuits are determined by the number of 1?s in the parity check matrix (PCM). The number of 1?s in the parity check matrix for the code proposed by the authors are fewer than in any currently known single error correcting/double error detecting code. This results in simplified encoding and decoding circuitry for error detection and correction.

Keywords: Decoder, Hsiao code, Parity Check Matrix, Syndrome Pattern.

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Authors: Mada Sanjaya, Halimatussadiyah, Dian Syah Maulana

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The nonlinear chaotic non-autonomous fourth order system is algebraically simple but can generate complex chaotic attractors. In this paper, non-autonomous fourth order chaotic oscillator circuits were designed and simulated. Also chaotic nonautonomous Attractor is addressed suitable for chaotic masking communication circuits using Matlab® and MultiSIM® programs. We have demonstrated in simulations that chaos can be synchronized and applied to signal masking communications. We suggest that this phenomenon of chaos synchronism may serve as the basis for little known chaotic non-autonomous Attractor to achieve signal masking communication applications. Simulation results are used to visualize and illustrate the effectiveness of non-autonomous chaotic system in signal masking. All simulations results performed on nonautonomous chaotic system are verify the applicable of secure communication.

Keywords: Bidirectional chaotic synchronization, double bellattractor, secure communication

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Authors: Zahra Khalid, Gul Muhammad Khan, Arbab Masood Ahmad

Abstract:

Cartesian Genetic Programming (CGP) is explored to design an optimal circuit capable of early stage breast cancer detection. CGP is used to evolve simple multiplexer circuits for detection of malignancy in the Fine Needle Aspiration (FNA) samples of breast. The data set used is extracted from Wisconsins Breast Cancer Database (WBCD). A range of experiments were performed, each with different set of network parameters. The best evolved network detected malignancy with an accuracy of 99.14%, which is higher than that produced with most of the contemporary non-linear techniques that are computational expensive than the proposed system. The evolved network comprises of simple multiplexers and can be implemented easily in hardware without any further complications or inaccuracy, being the digital circuit.

Keywords: Breast cancer detection, cartesian genetic programming, evolvable hardware, fine needle aspiration (FNA).

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