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Analysis of Effect of Pre-Logic Factoring on Cell Based Combinatorial Logic Synthesis

Authors: Padmanabhan Balasubramanian, Bashetty Raghavendra


In this paper, an analysis is presented, which demonstrates the effect pre-logic factoring could have on an automated combinational logic synthesis process succeeding it. The impact of pre-logic factoring for some arbitrary combinatorial circuits synthesized within a FPGA based logic design environment has been analyzed previously. This paper explores a similar effect, but with the non-regenerative logic synthesized using elements of a commercial standard cell library. On an overall basis, the results obtained pertaining to the analysis on a variety of MCNC/IWLS combinational logic benchmark circuits indicate that pre-logic factoring has the potential to facilitate simultaneous power, delay and area optimized synthesis solutions in many cases.

Keywords: low power, Algebraic factoring, Combinational logic synthesis, Standard cells, Delay optimization, Area reduction

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