Novel Linear Autozeroing Floating-gate Amplifier for Ultra Low-voltage Applications

Authors: Yngvar Berg, Mehdi Azadmehr

Abstract:

In this paper we present a linear autozeroing ultra lowvoltage amplifier. The autozeroing performed by all ULV circuits is important to reduce the impact of noise and especially avoid power supply noise in mixed signal low-voltage CMOS circuits. The simulated data presented is relevant for a 90nm TSMC CMOS process.

Keywords: Low-voltage, trans conductance amplifier, linearity, floating-gate.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1334724

References:

[1] Y. Berg, D. T. Wisland and T. S. Lande: "Ultra Low-Voltage/Low- Power Digital Floating-Gate Circuits", IEEE Transactions on Circuits and Systems, vol. 46, No. 7, pp. 930-936,july 1999.
[2] K. Kotani, T. Shibata, M. Imai and T. Ohmi. "Clocked-Neuron-MOS Logic Circuits Employing Auto-Threshold-Adjustment", In IEEE International Solid-State Circuits Conference (ISSCC), pp. 320-321,388, 1995.
[3] T. Shibata and T. Ohmi. " A Functional MOS Transistor Featuring Gate- Level Weighted Sum and Threshold Operations", In IEEE Transactions on Electron Devices, vol 39, 1992.
[4] Y. Berg and O. Mirmotahari: "Clocked Semi-Floating-Gate Ultra Low- Voltage Symmetric and Bidirectional Current Mirror", in Proc. IEEE Symposium on Design and Diagnostic of Electronic Systems (DDECS 2009), Liberec, Czech Republic, April 2009.
[5] Y. Berg and O. Mirmotahari: "Clocked Semi-Floating-Gate Pseudo Differential Pair for Low-Voltage Analog Design", In Proc. European Conference on Circuit Theory and Design (ECCTD-2009), Antalya, Turkey, August 2009.