Search results for: Reconfigurable devices.

Authors: M. Aqeel Iqbal

Abstract:

Fully customized hardware based technology provides high performance and low power consumption by specializing the tasks in hardware but lacks design flexibility since any kind of changes require re-design and re-fabrication. Software based solutions operate with software instructions due to which a great flexibility is achieved from the easy development and maintenance of the software code. But this execution of instructions introduces a high overhead in performance and area consumption. In past few decades the reconfigurable computing domain has been introduced which overcomes the traditional trades-off between flexibility and performance and is able to achieve high performance while maintaining a good flexibility. The dramatic gains in terms of chip performance and design flexibility achieved through the reconfigurable computing systems are greatly dependent on the design of their computational units being integrated with reconfigurable logic resources. The computational unit of any reconfigurable system plays vital role in defining its strength. In this research paper an RFU based computational unit design has been presented using the tightly coupled, multi-threaded reconfigurable cores. The proposed design has been simulated for VLIW based architectures and a high gain in performance has been observed as compared to the conventional computing systems.

Keywords: Configuration Stream, Configuration overhead, Configuration Controller, Reconfigurable devices.

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Authors: Aki Happonen, Adrian Burian, Erwin Hemming

Abstract:

Fixed-point simulation results are used for the performance measure of inverting matrices using a reconfigurable processing element. Matrices are inverted using the Cholesky decomposition algorithm. The reconfigurable processing element is capable of all required mathematical operations. The fixed-point word length analysis is based on simulations of different condition numbers and different matrix sizes.

Keywords: Cholesky Decomposition, Fixed-point, Matrixinversion, Reconfigurable processing.

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Authors: Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis

Abstract:

Speedups from mapping four real-life DSP applications on an embedded system-on-chip that couples coarsegrained reconfigurable logic with an instruction-set processor are presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elements. A design flow for improving application-s performance is proposed. Critical software parts, called kernels, are accelerated on the Coarse-Grained Reconfigurable Array. The kernels are detected by profiling the source code. For mapping the detected kernels on the reconfigurable logic a prioritybased mapping algorithm has been developed. Two 4x4 array architectures, which differ in their interconnection structure among the Processing Elements, are considered. The experiments for eight different instances of a generic system show that important overall application speedups have been reported for the four applications. The performance improvements range from 1.86 to 3.67, with an average value of 2.53, compared with an all-software execution. These speedups are quite close to the maximum theoretical speedups imposed by Amdahl-s law.

Keywords: Reconfigurable computing, Coarse-grained reconfigurable array, Embedded systems, DSP, Performance

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Authors: V. Nagaraju, Tapas Bapu. B. R, Beryl J. Victor

Abstract:

In this paper cognitive radio is presented and the spectrum overlay cognitive radio antenna system is detailed. A UWB antenna with frequency reconfigurable characteristics is proposed. The reconfigurability is achieved when the filter is integrated to the feeding line of the single port overlay cognitive radio. When activated, the filter can transform the UWB frequency response into a reconfigurable narrowband one, which is suitable for the communication operation of the CR system. Here single port overlay cognitive radio antenna is designed and simulated using Ansoft High Frequency Structure Simulator (HFSS).

Keywords: Band-pass filter, Cognitive radio, filtenna, frequency reconfigurable, ultra-wideband antenna.

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Authors: Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou

Abstract:

This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm² and dissipates 233.5 mW at maximal operating frequency of 250 MHz.

Keywords: Reconfigurable, fast Fourier transform, single-path delay feedback, 3GPP-LTE.

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Authors: Manpreet Singh, V. P. Agrawal, Gurmanjot Singh Bhatti

Abstract:

From the last decades, there is a significant technological advancement in the field of robotics, and a number of modular self-reconfigurable robots were introduced that can help in space exploration, bucket to stuff, search, and rescue operation during earthquake, etc. As there are numbers of self-reconfigurable robots, choosing the optimum one is always a concern for robot user since there is an increase in available features, facilities, complexity, etc. The objective of this research work is to present a multiple attribute decision making based methodology for coding, evaluation, comparison ranking and selection of modular self-reconfigurable robots using a technique for order preferences by similarity to ideal solution approach. However, 86 attributes that affect the structure and performance are identified. A database for modular self-reconfigurable robot on the basis of different pertinent attribute is generated. This database is very useful for the user, for selecting a robot that suits their operational needs. Two visual methods namely linear graph and spider chart are proposed for ranking of modular self-reconfigurable robots. Using five robots (Atron, Smores, Polybot, M-Tran 3, Superbot), an example is illustrated, and raking of the robots is successfully done, which shows that Smores is the best robot for the operational need illustrated, and this methodology is found to be very effective and simple to use.

Keywords: Self-reconfigurable robots, MADM, TOPSIS, morphogenesis, scalability.

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Authors: Qinghua Zhang, Yanhe Zhu, Xiang Zhao, Yeqin Yang, Hongwei Jing, Guoan Zhang, Jie Zhao

Abstract:

This paper presents a wearable reconfigurable supernumerary robotic limb with differential actuated joints, which is lightweight, compact and comfortable for the wearers. Compared to the existing supernumerary robotic limbs which mostly adopted series structure with large movement space but poor carrying capacity, a prototype with the series-parallel configuration to better adapt to different task requirements has been developed in this design. To achieve a compact structure, two kinds of cable-driven mechanical structures based on guide pulleys and differential actuated joints were designed. Moreover, two different tension devices were also designed to ensure the reliability and accuracy of the cable-driven transmission. The proposed device also employed self-designed bearings which greatly simplified the structure and reduced the cost.

Keywords: Cable-driven, differential actuated joints, reconfigurable, supernumerary robotic limb.

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Authors: Kahloul Laid, Chaoui Allaoua

Abstract:

Code mobility technologies attract more and more developers and consumers. Numerous domains are concerned, many platforms are developed and interest applications are realized. However, developing good software products requires modeling, analyzing and proving steps. The choice of models and modeling languages is so critical on these steps. Formal tools are powerful in analyzing and proving steps. However, poorness of classical modeling language to model mobility requires proposition of new models. The objective of this paper is to provide a specific formalism “Coloured Reconfigurable Nets" and to show how this one seems to be adequate to model different kinds of code mobility.

Keywords: Code mobility, modelling mobility, labelled reconfigurable nets, Coloured reconfigurable nets, mobile code design paradigms.

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Authors: Sasho Guergov

Abstract:

The purpose of the paper is to develop an informationcontrol environment for overall management and self-reconfiguration of the reconfigurable multifunctional machine tool for machining both rotation and prismatic parts and high concentration of different technological operations - turning, milling, drilling, grinding, etc. For the realization of this purpose on the basis of defined sub-processes for the implementation of the technological process, architecture of the information-search system for machine control is suggested. By using the object-oriented method, a structure and organization of the search system based on agents and manager with central control are developed. Thus conditions for identification of available information in DBs, self-reconfiguration of technological system and entire control of the reconfigurable multifunctional machine tool are created.

Keywords: Information system, multifunctional machine tool, reconfigurable machine tool, search system.

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Authors: G. Kalpanadevi, S. Ravimaran, M. Shanmugapriya

Abstract:

A Reconfigurable Wilkinson power divider is proposed in this paper. In existing system only a limited number of bandwidth is used at the output ports, in the proposed Wilkinson power divider different band of frequencies are obtained by using PIN diode. By tuning the PIN diode, different frequencies are achieved. The size of the power divider is reduced for the operating frequency and increases the fractional bandwidth.

Keywords: Isolation loss, PIN diode, Reconfigurable Wilkinson power divider and WLAN applications.

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Authors: Majid Tolouei-Rad

Abstract:

This paper presents methodologies for developing an intelligent CAD system assisting in analysis and design of reconfigurable special machines. It describes a procedure for determining feasibility of utilizing these machines for a given part and presents a model for developing an intelligent CAD system. The system analyzes geometrical and topological information of the given part to determine possibility of the part being produced by reconfigurable special machines from a technical point of view. Also feasibility of the process from a economical point of view is analyzed. Then the system determines proper positioning of the part considering details of machining features and operations needed. This involves determination of operation types, cutting tools and the number of working stations needed. Upon completion of this stage the overall layout of the machine and machining equipment required are determined.

Keywords: CAD, Knowledge based system, Reconfigurable

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Authors: Yibo Fan, Takeshi Ikenaga, Yukiyasu Tsunoo, Satoshi Goto

Abstract:

This paper proposes a low-cost reconfigurable architecture for AES algorithm. The proposed architecture separates SubBytes and MixColumns into two parallel data path, and supports different bit-width operation for this two data path. As a result, different number of S-box can be supported in this architecture. The throughput and power consumption can be adjusted by changing the number of S-box running in this design. Using the TSMC 0.18μm CMOS standard cell library, a very low-cost implementation of 7K Gates is obtained under 182MHz frequency. The maximum throughput is 360Mbps while using 4 S-Box simultaneously, and the minimum throughput is 114Mbps while only using 1 S-Box

Keywords: AES, Reconfigurable architecture, low cost

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Authors: Aki Happonen, Adrian Burian, Erwin Hemming

Abstract:

Fixed-point simulation results are used for the performance measure of inverting matrices by Cholesky decomposition. The fixed-point Cholesky decomposition algorithm is implemented using a fixed-point reconfigurable processing element. The reconfigurable processing element provides all mathematical operations required by Cholesky decomposition. The fixed-point word length analysis is based on simulations using different condition numbers and different matrix sizes. Simulation results show that 16 bits word length gives sufficient performance for small matrices with low condition number. Larger matrices and higher condition numbers require more dynamic range for a fixedpoint implementation.

Keywords: Cholesky Decomposition, Fixed-point, Matrix inversion, Reconfigurable processing.

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Authors: Gaurav Upadhyay, Nand Kishore, Prashant Ranjan, V. S. Tripathi, Shivesh Tripathi

Abstract:

A frequency reconfigurable multiband antenna for intelligent transportation system (ITS) applications is proposed in this paper. A PIN-diode is used for reconfigurability. Centre frequencies are 1.38, 1.98, 2.89, 3.86, and 4.34 GHz in “ON” state of Diode and 1.56, 2.16, 2.88, 3.91 and 4.45 GHz in “OFF” state. Achieved maximum bandwidth is 18%. The maximum gain of the proposed antenna is 2.7 dBi in “ON” state and 3.95 dBi in “OFF” state of the diode. The antenna is simulated, fabricated, and tested in the lab. Measured and simulated results are in good confirmation.

Keywords: ITS, multiband antenna, PIN-diode, reconfigurable.

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Authors: Roscoe McLean, Jared Padayachee, Glen Bright

Abstract:

There is currently a gap in the technology covering the rapid establishment of control after a reconfiguration in a Reconfigurable Manufacturing System. This gap involves the detection of the factory floor state and the communication link between the factory floor and the high-level software. In this paper, a thin, hardware-supported Middleware Management System (MMS) is proposed and its design and implementation are discussed. The research found that a cost-effective localization technique can be combined with intelligent software to speed up the ramp-up of a reconfigured system. The MMS makes the process more intelligent, more efficient and less time-consuming, thus supporting the industrial implementation of the RMS paradigm.

Keywords: Intelligent systems, middleware, reconfigurable manufacturing.

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Authors: Indumathi T. S., T. Srinivas, B. Siva Kumar

Abstract:

Reconfigurable optical add/drop multiplexers (ROADMs) can be classified into three categories based on their underlying switching technologies. Category I consists of a single large optical switch; category II is composed of a number of small optical switches aligned in parallel; and category III has a single optical switch and only one wavelength being added/dropped. In this paper, to evaluate the wavelength-routing capability of ROADMs of category-II in dynamic optical networks,the dynamic traffic models are designed based on Bernoulli, Poisson distributions for smooth and regular types of traffic. Through Analytical and Simulation results, the routing power of cat-II of ROADM networks for two traffic models are determined.

Keywords: Fully-Reconfigurable Optical Add-Drop Multiplexers (FROADMs), Limited Tunability in Reconfigurable Optical Add-Drop multiplexers (LROADM), Multiplexer/De- Multiplexer (MUX/DEMUX), Reconfigurable Optical Add-Drop Multiplexers (ROADMs), Wavelength Division Multiplexing (WDM).

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Authors: Cyrille Lambert, Tatiana Kalganova, Emanuele Stomeo, Manissa Wilson

Abstract:

A multi-board run-time reconfigurable (MRTR) system for evolvable hardware (EHW) is introduced with the aim to implement on hardware the bidirectional incremental evolution (BIE) method. The main features of this digital intrinsic EHW solution rely on the multi-board approach, the variable chromosome length management and the partial configuration of the reconfigurable circuit. These three features provide a high scalability to the solution. The design has been written in VHDL with the concern of not being platform dependant in order to keep a flexibility factor as high as possible. This solution helps tackling the problem of evolving complex task on digital configurable support.

Keywords: Evolvable Hardware, Evolutionary Strategy, multiboardFPGA system.

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Authors: Gaurav Upadhyay, Nand Kishore, Prashant Ranjan, Shivesh Tripathi, V. S. Tripathi

Abstract:

In this paper, a patch antenna array design is proposed for vehicular communication. The antenna consists of 2-element patch array. The antenna array is operating at multiple frequency bands. The multiband operation is achieved by use of slots at proper locations at the patch. The array is made reconfigurable by use of two PIN-diodes. The antenna is simulated and measured in four states of diodes i.e. ON-ON, ON-OFF, OFF-ON, and OFF-OFF. In ON-ON state of diodes, the resonant frequencies are 4.62-4.96, 6.50-6.75, 6.90-7.01, 7.34-8.22, 8.89-9.09 GHz. In ON-OFF state of diodes, the measured resonant frequencies are 4.63-4.93, 6.50-6.70 and 7.81-7.91 GHz. In OFF-ON states of diodes the resonant frequencies are 1.24-1.46, 3.40-3.75, 5.07-5.25 and 6.90-7.20 GHz and in the OFF-OFF state of diodes 4.49-4.75 and 5.61-5.98 GHz. The maximum bandwidth of the proposed antenna is 16.29%. The peak gain of the antenna is 3.4 dB at 5.9 GHz, which makes it suitable for vehicular communication.

Keywords: Antenna, array, reconfigurable, vehicular.

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Authors: Jae-Min Yu, Hyoung-Ho Doh, Ji-Su Kim, Dong-Ho Lee, Sung-Ho Nam

Abstract:

A reconfigurable manufacturing system (RMS) is an advanced system designed at the outset for rapid changes in its hardware and software components in order to quickly adjust its production capacity and functionally. Among various operational decisions, this study considers the scheduling problem that determines the input sequence and schedule at the same time for a given set of parts. In particular, we consider the practical constraints that the numbers of pallets/fixtures are limited and hence a part can be released into the system only when the fixture required for the part is available. To solve the integrated input sequencing and scheduling problems, we suggest a priority rule based approach in which the two sub-problems are solved using a combination of priority rules. To show the effectiveness of various rule combinations, a simulation experiment was done on the data for a real RMS, and the test results are reported.

Keywords: Reconfigurable manufacturing system, scheduling, priority rules, multiple process plans, pallets/fixtures

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Authors: Sudhina H. K, Ravi M. Yadahalli, N. M. Shetti

Abstract:

Reconfigurable antennas represent a recent innovation in antenna design that changes from classical fixed-form, fixed function antennas to modifiable structures that can be adapted to fit the requirements of a time varying system.

The ability to control the operating band of an antenna system can have many useful applications. Systems that operate in an acquire-and-track configuration would see a benefit from active bandwidth control. In such systems a wide band search mode is first employed to find a desired signal then a narrow band track mode is used to follow only that signal. Utilizing active antenna bandwidth control, a single antenna would function for both the wide band and narrow band configurations providing the rejection of unwanted signals with the antenna hardware. This ability to move a portion of the RF filtering out of the receiver and onto the antenna itself will also aid in reducing the complexity of the often expensive RF processing subsystems.

Keywords: Designing methods, MEMS, stack, reconfigurable elements.

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Authors: A. Pedram, M. R. Jamali, T. Pedram, S. M. Fakhraie, C. Lucas

Abstract:

Local Linear Neuro-Fuzzy Models (LLNFM) like other neuro- fuzzy systems are adaptive networks and provide robust learning capabilities and are widely utilized in various applications such as pattern recognition, system identification, image processing and prediction. Local linear model tree (LOLIMOT) is a type of Takagi-Sugeno-Kang neuro fuzzy algorithm which has proven its efficiency compared with other neuro fuzzy networks in learning the nonlinear systems and pattern recognition. In this paper, a dedicated reconfigurable and parallel processing hardware for LOLIMOT algorithm and its applications are presented. This hardware realizes on-chip learning which gives it the capability to work as a standalone device in a system. The synthesis results on FPGA platforms show its potential to improve the speed at least 250 of times faster than software implemented algorithms.

Keywords: LOLIMOT, hardware, neurofuzzy systems, reconfigurable, parallel.

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Authors: Lakhdar Zaid, Albane Sangiovanni

Abstract:

A reconfigurable microstrip patch antenna with polyphase filter for polarization diversity and cross polarization filtering operation is presented in this paper. In our approach, a polyphase filter is used to obtain the four 90° phase shift outputs to feed a square microstrip patch antenna. The antenna can be switched between four states of polarization in transmission as well as in receiving mode. Switches are interconnected with the polyphase filter network to produce left-hand circular polarization, right-hand circular polarization, horizontal linear polarization, and vertical linear polarization. Additional advantage of using polyphase filter is its filtering capability for cross polarization filtering in right-hand circular polarization and left-hand circular polarization operation. The theoretical and simulated results demonstrated that polyphase filter is a good candidate to drive microstrip patch antenna to accomplish polarization diversity and cross polarization filtering operation.

Keywords: Microstrip patch antenna, polyphase filter, circular polarization, linear polarization, reconfigurable antenna.

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Authors: M. Javid Asad, M. Zafrullah, Mian Shahzad Iqbal

Abstract:

In this research paper, a slotted coaxial line fed cross dipole excitation structure for short backfire antenna is proposed and developed to achieve reconfigurable circular polarization. The cross dipole, which is fed by the slotted coaxial line, consists of two orthogonal dipoles. The dipoles are mounted on the outer conductor of the coaxial line. A unique technique is developed to generate reconfigurable circular polarization using cross dipole configuration. The sub-reflector is supported by the feed line, thus requiring no extra support. The antenna is developed on elliptical ground plane with dielectric rim making antenna compact. It is demonstrated that cross dipole excited short backfire antenna can achieve voltage standing wave ratio (VSWR) bandwidth of 14.28% for 2:1 VSWR, axial ratio of 0.2 dB with axial ratio (≤ 3dB) bandwidth of 2.14% and a gain of more than 12 dBi. The experimental results for the designed antenna structure are in close agreement with computer simulations.

Keywords: Circularly polarized, compact, short backfireantenna.

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Authors: Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis

Abstract:

Modern applications realized onto FPGAs exhibit high connectivity demands. Throughout this paper we study the routing constraints of Virtex devices and we propose a systematic methodology for designing a novel general-purpose interconnection network targeting to reconfigurable architectures. This network consists of multiple segment wires and SB patterns, appropriately selected and assigned across the device. The goal of our proposed methodology is to maximize the hardware utilization of fabricated routing resources. The derived interconnection scheme is integrated on a Virtex style FPGA. This device is characterized both for its high-performance, as well as for its low-energy requirements. Due to this, the design criterion that guides our architecture selections was the minimal Energy×Delay Product (EDP). The methodology is fully-supported by three new software tools, which belong to MEANDER Design Framework. Using a typical set of MCNC benchmarks, extensive comparison study in terms of several critical parameters proves the effectiveness of the derived interconnection network. More specifically, we achieve average Energy×Delay Product reduction by 63%, performance increase by 26%, reduction in leakage power by 21%, reduction in total energy consumption by 11%, at the expense of increase of channel width by 20%.

Keywords: Design Methodology, FPGA, Interconnection, Low-Energy, High-Performance, CAD tool.

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Authors: Haruo Shimada, Akinori Kanasugi

Abstract:

This paper proposes an architecture of dynamically reconfigurable arithmetic circuit. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operations. The proposed circuit is based on a complex number multiply-accumulation circuit which is used frequently in the field of digital signal processing. In addition, the proposed circuit performs real number double precision arithmetic operations. The data formats are single and double precision floating point number based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

Keywords: arithmetic circuit, complex number, double precision, dynamic reconfiguration

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Authors: Chi-Yan Chu, Kai-Chi Chuang, Huang-Chung Cheng

Abstract:

In this study, the RRAM devices with the TiN/Ti/HfO_x/TiN structure were fabricated, then the electrical characteristics of the devices without annealing and after 400 °C and 500 °C of the furnace annealing (FA) temperature processes were compared. The RRAM devices after the FA’s 400 °C showed the lower forming, set and reset voltages than the other devices without annealing. However, the RRAM devices after the FA’s 500 °C did not show any electrical characteristics because the TiN/Ti/HfO_x/TiN device was oxidized, as shown in the XPS analysis. From these results, the RRAM devices after the FA’s 400 °C showed the best electrical characteristics.

Keywords: RRAM, furnace annealing, forming, set and reset voltages, XPS.

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Authors: A. B.Bhattacharyya, B. S.K.Goswami

Abstract:

This paper presents Genetic Algorithm (GA) based approach for the allocation of FACTS (Flexible AC Transmission System) devices for the improvement of Power transfer capacity in an interconnected Power System. The GA based approach is applied on IEEE 30 BUS System. The system is reactively loaded starting from base to 200% of base load. FACTS devices are installed in the different locations of the power system and system performance is noticed with and without FACTS devices. First, the locations, where the FACTS devices to be placed is determined by calculating active and reactive power flows in the lines. Genetic Algorithm is then applied to find the amount of magnitudes of the FACTS devices. This approach of GA based placement of FACTS devices is tremendous beneficial both in terms of performance and economy is clearly observed from the result obtained.

Keywords: FACTS Devices, Line Power Flow, OptimalLocation of FACTS Devices, Genetic Algorithm.

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Authors: Daniela I. Borissova, Ivan C. Mustakerov

Abstract:

The paper describes an approach for defining of k-best night vision devices based on multi-criteria mixed-integer optimization modeling. The parameters of night vision devices are considered as criteria that have to be optimized. Using different user preferences for the relative importance between parameters different choice of k-best devices can be defined. An ideal device with all of its parameters at their optimum is used to determine how far the particular device from the ideal one is. A procedure for evaluation of deviation between ideal solution and k-best solutions is presented. The applicability of the proposed approach is numerically illustrated using real night vision devices data. The proposed approach contributes to quality of decisions about choice of night vision devices by making the decision making process more certain, rational and efficient. 

Keywords: K-best devices, mixed-integer model, multi-criteria problem, night vision devices.

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Authors: Qian Wang, Sylvain Lassalle, Antony R. Mileham, Geraint W. Owen

Abstract:

This paper mathematically analyses the varying magnitude of production loss, which may occur due to idle time (inprocess waiting time and traveling time) on a linear walking worker assembly line. Within this flexible and reconfigurable assembly system, each worker travels down the line carrying out each assembly task at each station; and each worker accomplishes the assembly of a unit from start to finish and then travels back to the first station to start the assembly of a new product. This strategy of system design attempts to combine the flexibility of the U-shaped moving worker assembly cell with the efficiency of the conventional fixed worker assembly line. The paper aims to evaluate the effect of idle time that may offset the labor efficiency of each walking worker providing an insight into the mechanism of such a flexible and reconfigurable assembly system.

Keywords: Production lines, manufacturing systems, assemblysystems, walking workers.

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Authors: Raed A. Amro

Abstract:

Standard packaging and interconnection technologies of power devices have difficulties meeting the increasing thermal demands of new application fields of power electronics devices. Main restrictions are the decreasing reliability of bond-wires and solder layers with increasing junction temperature. In the last few years intensive efforts have been invested in developing new packaging and interconnection solutions which may open a path to future application of power devices. In this paper, the main failure mechanisms of power devices are described and principle of new packaging and interconnection concepts and their power cycling reliability are presented.

Keywords: Power electronics devices, Reliability, Power Cycling, Low-temperature joining technique (LTJT)

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