%0 Journal Article %A Yibo Fan and Takeshi Ikenaga and Yukiyasu Tsunoo and Satoshi Goto %D 2008 %J International Journal of Computer and Information Engineering %B World Academy of Science, Engineering and Technology %I Open Science Index 17, 2008 %T A Low-cost Reconfigurable Architecture for AES Algorithm %U https://publications.waset.org/pdf/234 %V 17 %X This paper proposes a low-cost reconfigurable architecture for AES algorithm. The proposed architecture separates SubBytes and MixColumns into two parallel data path, and supports different bit-width operation for this two data path. As a result, different number of S-box can be supported in this architecture. The throughput and power consumption can be adjusted by changing the number of S-box running in this design. Using the TSMC 0.18μm CMOS standard cell library, a very low-cost implementation of 7K Gates is obtained under 182MHz frequency. The maximum throughput is 360Mbps while using 4 S-Box simultaneously, and the minimum throughput is 114Mbps while only using 1 S-Box %P 1687 - 1690